multrow.v

来自「64位乘法器源码verilog,经过验证测试」· Verilog 代码 · 共 18 行

module multrow(part,x,ym,yo,cin,s,cout);
    /* A row of one-bit multiplies */
    input [6:0] part;
    input [7:0] x;
    input ym, yo;
    input [6:0] cin;
    output [6:0] s;
    output [6:0] cout;

   assign {cout[0],s[0]} = part[1] + (x[0] & ym) + cin[0];
   assign {cout[1],s[1]} = part[2] + (x[1] & ym) + cin[1];
   assign {cout[2],s[2]} = part[3] + (x[2] & ym) + cin[2];
   assign {cout[3],s[3]} = part[4] + (x[3] & ym) + cin[3];
   assign {cout[4],s[4]} = part[5] + (x[4] & ym) + cin[4];
   assign {cout[5],s[5]} = part[6] + (x[5] & ym) + cin[5];
   assign {cout[6],s[6]} = (x[7] & yo) + (x[6] & ym) + cin[6];
endmodule