mult_s.v

来自「64位乘法器源码verilog,经过验证测试」· Verilog 代码 · 共 9 行

module mult_s(x,y,p);
    input signed [7:0] x;
    input signed [7:0] y;
    output [15:0] p;

assign p = x*y;

endmodule