boothcode.v

来自「64位乘法器源码verilog,经过验证测试」· Verilog 代码 · 共 59 行

module boothcode(x,op,sel);

    input [2:0] x;
    output op;
    output [1:0] sel;

	 reg op_tmp; 
	 reg [1:0] sel_tmp;

	 always @(x)
	  begin
	   case (x)
		  3'b000:  
		    begin
			   op_tmp=0;  sel_tmp=2'b00;
  			 end

		  3'b001: 
		    begin
			   op_tmp=0; sel_tmp=2'b01;
          end

		  3'b010: 
		    begin
			   op_tmp=0; sel_tmp=2'b01;
          end

		  3'b011: 
		    begin
			   op_tmp=0; sel_tmp=2'b10;
          end

		  3'b100: 
		    begin
			   op_tmp=1; sel_tmp=2'b10;
          end

		  3'b101: 
		    begin
			   op_tmp=1; sel_tmp=2'b01;
          end

		  3'b110: 
		    begin
			   op_tmp=1; sel_tmp=2'b01;
          end

		  3'b111: 
		    begin
			   op_tmp=0; sel_tmp=2'b00;
          end
		endcase
	  end

	  assign op = op_tmp;
	  assign sel = sel_tmp;

endmodule