multcell.v

来自「64位乘法器源码verilog,经过验证测试」· Verilog 代码 · 共 13 行

module multcell(part,x,y,cin,s,cout);
    input part; /* result from cell above */
    input x; /* a bit to multiply */
    input y; /* b bit to multiply */
    input cin; /* carry in */
    output s; /* sum */
    output cout; /* carryout */ 
    wire andbits;

    assign andbits = x & y; /* generate the product of two input bits */
    fulladd add0(part,andbits,cin,s,cout); /* perform the addition */
endmodule