bw_mult.v

来自「64位乘法器源码verilog,经过验证测试」· Verilog 代码 · 共 24 行

module bw_mult(x,y,p);
    input [7:0] x;
    input [7:0] y;
    output [14:0] p;


wire [6:0]  x7_ext = {x[7], x[7], x[7], x[7], x[7], x[7], x[7]};
wire [6:0]  y7_ext = {y[7], y[7], y[7], y[7], y[7], y[7], y[7]};

wire [6:0] x7y = x7_ext & y[6:0];
wire [6:0] y7x = y7_ext & x[6:0];
wire [7:0] m = x7y[6:0] + y7x;

wire x7y7 = x[7] & y[7];
wire [13:0] p1 = x[6:0]*y[6:0];
wire [14:0] p2 = {x7y7, p1};

wire [7:0] d = p2[14:7] - m;

assign p = {d, p2[6:0]}; 


endmodule