i8051_lib.map.rpt

来自「8051的vhdl源代码」· RPT 代码 · 共 135 行

Analysis & Synthesis report for i8051_lib
Fri Jun 06 09:40:12 2008
Quartus II Version 7.1 Build 156 04/30/2007 SJ Full Version


---------------------
; Table of Contents ;
---------------------
  1. Legal Notice
  2. Analysis & Synthesis Summary
  3. Analysis & Synthesis Settings
  4. Analysis & Synthesis Messages



----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2007 Altera Corporation
Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic 
functions, and any output files from any of the foregoing 
(including device programming or simulation files), and any 
associated documentation or information are expressly subject 
to the terms and conditions of the Altera Program License 
Subscription Agreement, Altera MegaCore Function License 
Agreement, or other applicable license agreement, including, 
without limitation, that your use is for the sole purpose of 
programming logic devices manufactured by Altera and sold by 
Altera or its authorized distributors.  Please refer to the 
applicable agreement for further details.



+-------------------------------------------------------------------------------+
; Analysis & Synthesis Summary                                                  ;
+------------------------------------+------------------------------------------+
; Analysis & Synthesis Status        ; Failed - Fri Jun 06 09:40:12 2008        ;
; Quartus II Version                 ; 7.1 Build 156 04/30/2007 SJ Full Version ;
; Revision Name                      ; i8051_lib                                ;
; Top-level Entity Name              ; i8051_lib                                ;
; Family                             ; Cyclone II                               ;
; Total logic elements               ; N/A until Partition Merge                ;
;     Total combinational functions  ; N/A until Partition Merge                ;
;     Dedicated logic registers      ; N/A until Partition Merge                ;
; Total registers                    ; N/A until Partition Merge                ;
; Total pins                         ; N/A until Partition Merge                ;
; Total virtual pins                 ; N/A until Partition Merge                ;
; Total memory bits                  ; N/A until Partition Merge                ;
; Embedded Multiplier 9-bit elements ; N/A until Partition Merge                ;
; Total PLLs                         ; N/A until Partition Merge                ;
+------------------------------------+------------------------------------------+


+--------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Settings                                                                                            ;
+--------------------------------------------------------------------------------+--------------------+--------------------+
; Option                                                                         ; Setting            ; Default Value      ;
+--------------------------------------------------------------------------------+--------------------+--------------------+
; Device                                                                         ; EP2C8Q208C8        ;                    ;
; Top-level entity name                                                          ; i8051_lib          ; i8051_lib          ;
; Family name                                                                    ; Cyclone II         ; Stratix II         ;
; Restructure Multiplexers                                                       ; Auto               ; Auto               ;
; Create Debugging Nodes for IP Cores                                            ; Off                ; Off                ;
; Preserve fewer node names                                                      ; On                 ; On                 ;
; Disable OpenCore Plus hardware evaluation                                      ; Off                ; Off                ;
; Verilog Version                                                                ; Verilog_2001       ; Verilog_2001       ;
; VHDL Version                                                                   ; VHDL93             ; VHDL93             ;
; State Machine Processing                                                       ; Auto               ; Auto               ;
; Safe State Machine                                                             ; Off                ; Off                ;
; Extract Verilog State Machines                                                 ; On                 ; On                 ;
; Extract VHDL State Machines                                                    ; On                 ; On                 ;
; Ignore Verilog initial constructs                                              ; Off                ; Off                ;
; Add Pass-Through Logic to Inferred RAMs                                        ; On                 ; On                 ;
; DSP Block Balancing                                                            ; Auto               ; Auto               ;
; NOT Gate Push-Back                                                             ; On                 ; On                 ;
; Power-Up Don't Care                                                            ; On                 ; On                 ;
; Remove Redundant Logic Cells                                                   ; Off                ; Off                ;
; Remove Duplicate Registers                                                     ; On                 ; On                 ;
; Ignore CARRY Buffers                                                           ; Off                ; Off                ;
; Ignore CASCADE Buffers                                                         ; Off                ; Off                ;
; Ignore GLOBAL Buffers                                                          ; Off                ; Off                ;
; Ignore ROW GLOBAL Buffers                                                      ; Off                ; Off                ;
; Ignore LCELL Buffers                                                           ; Off                ; Off                ;
; Ignore SOFT Buffers                                                            ; On                 ; On                 ;
; Limit AHDL Integers to 32 Bits                                                 ; Off                ; Off                ;
; Optimization Technique -- Cyclone II/Cyclone III                               ; Balanced           ; Balanced           ;
; Carry Chain Length -- Stratix/Stratix GX/Cyclone/MAX II/Cyclone II/Cyclone III ; 70                 ; 70                 ;
; Auto Carry Chains                                                              ; On                 ; On                 ;
; Auto Open-Drain Pins                                                           ; On                 ; On                 ;
; Perform WYSIWYG Primitive Resynthesis                                          ; Off                ; Off                ;
; Perform gate-level register retiming                                           ; Off                ; Off                ;
; Allow register retiming to trade off Tsu/Tco with Fmax                         ; On                 ; On                 ;
; Auto ROM Replacement                                                           ; On                 ; On                 ;
; Auto RAM Replacement                                                           ; On                 ; On                 ;
; Auto Shift Register Replacement                                                ; Auto               ; Auto               ;
; Auto Clock Enable Replacement                                                  ; On                 ; On                 ;
; Allow Synchronous Control Signals                                              ; On                 ; On                 ;
; Force Use of Synchronous Clear Signals                                         ; Off                ; Off                ;
; Auto RAM to Logic Cell Conversion                                              ; Off                ; Off                ;
; Auto Resource Sharing                                                          ; Off                ; Off                ;
; Allow Any RAM Size For Recognition                                             ; Off                ; Off                ;
; Allow Any ROM Size For Recognition                                             ; Off                ; Off                ;
; Allow Any Shift Register Size For Recognition                                  ; Off                ; Off                ;
; Ignore translate_off and synthesis_off directives                              ; Off                ; Off                ;
; Show Parameter Settings Tables in Synthesis Report                             ; On                 ; On                 ;
; Ignore Maximum Fan-Out Assignments                                             ; Off                ; Off                ;
; Retiming Meta-Stability Register Sequence Length                               ; 2                  ; 2                  ;
; PowerPlay Power Optimization                                                   ; Normal compilation ; Normal compilation ;
; HDL message level                                                              ; Level2             ; Level2             ;
; Suppress Register Optimization Related Messages                                ; Off                ; Off                ;
; Number of Removed Registers Reported in Synthesis Report                       ; 100                ; 100                ;
; Clock MUX Protection                                                           ; On                 ; On                 ;
; Use smart compilation                                                          ; Off                ; Off                ;
+--------------------------------------------------------------------------------+--------------------+--------------------+


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 7.1 Build 156 04/30/2007 SJ Full Version
    Info: Processing started: Fri Jun 06 09:40:11 2008
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off i8051_lib -c i8051_lib
Info: Found 1 design units, including 0 entities, in source file my_lib/i8051_lib.vhd
    Info: Found design unit 1: I8051_LIB
Error: Top-level design entity "i8051_lib" is undefined
Error: Quartus II Analysis & Synthesis was unsuccessful. 1 error, 0 warnings
    Info: Allocated 147 megabytes of memory during processing
    Error: Processing ended: Fri Jun 06 09:40:12 2008
    Error: Elapsed time: 00:00:01