i8051_all_tb.vhd.bak

来自「8051的vhdl源代码」· BAK 代码 · 共 80 行

BAK
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LIBRARY ieee  ; LIBRARY work  ; USE ieee.std_logic_1164.all  ; USE ieee.std_logic_arith.all  ; USE work.i8051_lib.all  ; ENTITY i8051_all_tb  IS END ;  ARCHITECTURE i8051_all_tb_arch OF i8051_all_tb IS  SIGNAL p2_in   :  unsigned (7 downto 0)  ;   SIGNAL rst   :  std_logic  ;   SIGNAL xrm_addr   :  unsigned (15 downto 0)  ;   SIGNAL xrm_rd   :  std_logic  ;   SIGNAL xrm_out_data   :  unsigned (7 downto 0)  ;   SIGNAL p0_out   :  unsigned (7 downto 0)  ;   SIGNAL p1_in   :  unsigned (7 downto 0)  ;   SIGNAL p1_out   :  unsigned (7 downto 0)  ;   SIGNAL p3_in   :  unsigned (7 downto 0)  ;   SIGNAL p2_out   :  unsigned (7 downto 0)  ;   SIGNAL p3_out   :  unsigned (7 downto 0)  ;   SIGNAL clk   :  std_logic  ;   SIGNAL xrm_in_data   :  unsigned (7 downto 0)  ;   SIGNAL p0_in   :  unsigned (7 downto 0)  ;   SIGNAL xrm_wr   :  std_logic  ;   COMPONENT i8051_all      PORT (       p2_in  : in unsigned (7 downto 0) ;       rst  : in std_logic ;       xrm_addr  : out unsigned (15 downto 0) ;       xrm_rd  : out std_logic ;       xrm_out_data  : out unsigned (7 downto 0) ;       p0_out  : out unsigned (7 downto 0) ;       p1_in  : in unsigned (7 downto 0) ;       p1_out  : out unsigned (7 downto 0) ;       p3_in  : in unsigned (7 downto 0) ;       p2_out  : out unsigned (7 downto 0) ;       p3_out  : out unsigned (7 downto 0) ;       clk  : in std_logic ;       xrm_in_data  : in unsigned (7 downto 0) ;       p0_in  : in unsigned (7 downto 0) ;       xrm_wr  : out std_logic );   END COMPONENT ; BEGIN  DUT  : i8051_all      PORT MAP (       p2_in   => p2_in  ,      rst   => rst  ,      xrm_addr   => xrm_addr  ,      xrm_rd   => xrm_rd  ,      xrm_out_data   => xrm_out_data  ,      p0_out   => p0_out  ,      p1_in   => p1_in  ,      p1_out   => p1_out  ,      p3_in   => p3_in  ,      p2_out   => p2_out  ,      p3_out   => p3_out  ,      clk   => clk  ,      xrm_in_data   => xrm_in_data  ,      p0_in   => p0_in  ,      xrm_wr   => xrm_wr   ) ;--********* process is       begin          clk<='0';          wait for 25 ns;          clk<='1';          wait for 25 ns;      end process;--*********   process is       begin           rst<='1';           wait for 50 ns;           rst<='0';           wait for 200 ns;           wait;       end process;END ; 

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