i8051_all.fit.rpt

8051的vhdl源代码

; Fitter Settings                                                                                                                         ;
+-----------------------------------------------------------------------+--------------------------------+--------------------------------+
; Option                                                                ; Setting                        ; Default Value                  ;
+-----------------------------------------------------------------------+--------------------------------+--------------------------------+
; Device                                                                ; EP2C8Q208C8                    ;                                ;
; Fit Attempts to Skip                                                  ; 0                              ; 0.0                            ;
; Always Enable Input Buffers                                           ; Off                            ; Off                            ;
; Router Timing Optimization Level                                      ; Normal                         ; Normal                         ;
; Placement Effort Multiplier                                           ; 1.0                            ; 1.0                            ;
; Router Effort Multiplier                                              ; 1.0                            ; 1.0                            ;
; Optimize Hold Timing                                                  ; IO Paths and Minimum TPD Paths ; IO Paths and Minimum TPD Paths ;
; Optimize Fast-Corner Timing                                           ; Off                            ; Off                            ;
; PowerPlay Power Optimization                                          ; Normal compilation             ; Normal compilation             ;
; Optimize Timing                                                       ; Normal compilation             ; Normal compilation             ;
; Optimize IOC Register Placement for Timing                            ; On                             ; On                             ;
; Limit to One Fitting Attempt                                          ; Off                            ; Off                            ;
; Final Placement Optimizations                                         ; Automatically                  ; Automatically                  ;
; Fitter Aggressive Routability Optimizations                           ; Automatically                  ; Automatically                  ;
; Fitter Initial Placement Seed                                         ; 1                              ; 1                              ;
; PCI I/O                                                               ; Off                            ; Off                            ;
; Weak Pull-Up Resistor                                                 ; Off                            ; Off                            ;
; Enable Bus-Hold Circuitry                                             ; Off                            ; Off                            ;
; Auto Global Memory Control Signals                                    ; Off                            ; Off                            ;
; Auto Packed Registers -- Stratix II/II GX/III Cyclone II/III Arria GX ; Auto                           ; Auto                           ;
; Auto Delay Chains                                                     ; On                             ; On                             ;
; Auto Merge PLLs                                                       ; On                             ; On                             ;
; Ignore PLL Mode When Merging PLLs                                     ; Off                            ; Off                            ;
; Perform Physical Synthesis for Combinational Logic for Fitting        ; Off                            ; Off                            ;
; Perform Physical Synthesis for Combinational Logic for Performance    ; Off                            ; Off                            ;
; Perform Register Duplication for Performance                          ; Off                            ; Off                            ;
; Perform Logic to Memory Mapping for Fitting                           ; Off                            ; Off                            ;
; Perform Register Retiming for Performance                             ; Off                            ; Off                            ;
; Perform Asynchronous Signal Pipelining                                ; Off                            ; Off                            ;
; Fitter Effort                                                         ; Auto Fit                       ; Auto Fit                       ;
; Physical Synthesis Effort Level                                       ; Normal                         ; Normal                         ;
; Auto Global Clock                                                     ; On                             ; On                             ;
; Auto Global Register Control Signals                                  ; On                             ; On                             ;
; Stop After Congestion Map Generation                                  ; Off                            ; Off                            ;
; Save Intermediate Fitting Results                                     ; Off                            ; Off                            ;
; Use smart compilation                                                 ; Off                            ; Off                            ;
+-----------------------------------------------------------------------+--------------------------------+--------------------------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fitter Netlist Optimizations                                                                                                                                                               ;
+------------------------------+-----------------+------------------+---------------------+-----------+-------------------------------------------------------------------+------------------+
; Node                         ; Action          ; Operation        ; Reason              ; Node Port ; Destination Node                                                  ; Destination Port ;
+------------------------------+-----------------+------------------+---------------------+-----------+-------------------------------------------------------------------+------------------+
; I8051_CTR:U_CTR|alu_src_2[0] ; Packed Register ; Register Packing ; Timing optimization ; REGOUT    ; I8051_ALU:U_ALU|lpm_mult:Mult0|mult_cs01:auto_generated|mac_mult1 ; DATAB            ;
; I8051_CTR:U_CTR|alu_src_2[0] ; Duplicated      ; Register Packing ; Timing optimization ; REGOUT    ; I8051_CTR:U_CTR|alu_src_2[0]~_Duplicate_1                         ; REGOUT           ;
; I8051_CTR:U_CTR|alu_src_2[1] ; Packed Register ; Register Packing ; Timing optimization ; REGOUT    ; I8051_ALU:U_ALU|lpm_mult:Mult0|mult_cs01:auto_generated|mac_mult1 ; DATAB            ;
; I8051_CTR:U_CTR|alu_src_2[1] ; Duplicated      ; Register Packing ; Timing optimization ; REGOUT    ; I8051_CTR:U_CTR|alu_src_2[1]~_Duplicate_1                         ; REGOUT           ;
; I8051_CTR:U_CTR|alu_src_2[2] ; Packed Register ; Register Packing ; Timing optimization ; REGOUT    ; I8051_ALU:U_ALU|lpm_mult:Mult0|mult_cs01:auto_generated|mac_mult1 ; DATAB            ;
; I8051_CTR:U_CTR|alu_src_2[2] ; Duplicated      ; Register Packing ; Timing optimization ; REGOUT    ; I8051_CTR:U_CTR|alu_src_2[2]~_Duplicate_1                         ; REGOUT           ;
; I8051_CTR:U_CTR|alu_src_2[3] ; Packed Register ; Register Packing ; Timing optimization ; REGOUT    ; I8051_ALU:U_ALU|lpm_mult:Mult0|mult_cs01:auto_generated|mac_mult1 ; DATAB            ;
; I8051_CTR:U_CTR|alu_src_2[3] ; Duplicated      ; Register Packing ; Timing optimization ; REGOUT    ; I8051_CTR:U_CTR|alu_src_2[3]~_Duplicate_1                         ; REGOUT           ;
; I8051_CTR:U_CTR|alu_src_2[4] ; Packed Register ; Register Packing ; Timing optimization ; REGOUT    ; I8051_ALU:U_ALU|lpm_mult:Mult0|mult_cs01:auto_generated|mac_mult1 ; DATAB            ;
; I8051_CTR:U_CTR|alu_src_2[4] ; Duplicated      ; Register Packing ; Timing optimization ; REGOUT    ; I8051_CTR:U_CTR|alu_src_2[4]~_Duplicate_1                         ; REGOUT           ;
; I8051_CTR:U_CTR|alu_src_2[5] ; Packed Register ; Register Packing ; Timing optimization ; REGOUT    ; I8051_ALU:U_ALU|lpm_mult:Mult0|mult_cs01:auto_generated|mac_mult1 ; DATAB            ;
; I8051_CTR:U_CTR|alu_src_2[5] ; Duplicated      ; Register Packing ; Timing optimization ; REGOUT    ; I8051_CTR:U_CTR|alu_src_2[5]~_Duplicate_1                         ; REGOUT           ;
; I8051_CTR:U_CTR|alu_src_2[6] ; Packed Register ; Register Packing ; Timing optimization ; REGOUT    ; I8051_ALU:U_ALU|lpm_mult:Mult0|mult_cs01:auto_generated|mac_mult1 ; DATAB            ;
; I8051_CTR:U_CTR|alu_src_2[6] ; Duplicated      ; Register Packing ; Timing optimization ; REGOUT    ; I8051_CTR:U_CTR|alu_src_2[6]~_Duplicate_1                         ; REGOUT           ;
; I8051_CTR:U_CTR|alu_src_2[7] ; Packed Register ; Register Packing ; Timing optimization ; REGOUT    ; I8051_ALU:U_ALU|lpm_mult:Mult0|mult_cs01:auto_generated|mac_mult1 ; DATAB            ;
; I8051_CTR:U_CTR|alu_src_2[7] ; Duplicated      ; Register Packing ; Timing optimization ; REGOUT    ; I8051_CTR:U_CTR|alu_src_2[7]~_Duplicate_1                         ; REGOUT           ;
+------------------------------+-----------------+------------------+---------------------+-----------+-------------------------------------------------------------------+------------------+


+--------------+
; Pin-Out File ;
+--------------+
The pin-out file can be found in D:/8051/i8051_all.pin.


+---------------------------------------------------------------------------+
; Fitter Resource Usage Summary                                             ;
+---------------------------------------------+-----------------------------+
; Resource                                    ; Usage                       ;
+---------------------------------------------+-----------------------------+
; Total logic elements                        ; 5,629 / 8,256 ( 68 % )      ;
;     -- Combinational with no register       ; 4274                        ;
;     -- Register only                        ; 11                          ;
;     -- Combinational with a register        ; 1344                        ;
;                                             ;                             ;
; Logic element usage by number of LUT inputs ;                             ;
;     -- 4 input functions                    ; 4539                        ;
;     -- 3 input functions                    ; 891                         ;