📄 div.vhd
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-- megafunction wizard: %ALTFP_DIV%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: altfp_div
-- ============================================================
-- File Name: div.vhd
-- Megafunction Name(s):
-- altfp_div
--
-- Simulation Library Files(s):
-- altera_mf;lpm
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 7.1 Build 156 04/30/2007 SJ Full Version
-- ************************************************************
--Copyright (C) 1991-2007 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
--altfp_div CBX_AUTO_BLACKBOX="ALL" DECODER_SUPPORT="NO" DENORMAL_SUPPORT="NO" DEVICE_FAMILY="Cyclone II" EXCEPTION_HANDLING="YES" PIPELINE=33 REDUCED_FUNCTIONALITY="YES" WIDTH_EXP=8 WIDTH_MAN=23 clock dataa datab division_by_zero nan overflow result underflow
--VERSION_BEGIN 7.1 cbx_altbarrel_shift 2006:08:31:00:41:52:SJ cbx_altfp_div 2007:03:01:19:17:12:SJ cbx_altsyncram 2007:03:22:08:29:24:SJ cbx_cycloneii 2007:01:23:09:39:40:SJ cbx_lpm_abs 2006:04:25:14:52:42:SJ cbx_lpm_add_sub 2007:01:08:11:15:18:SJ cbx_lpm_compare 2007:02:05:11:33:54:SJ cbx_lpm_decode 2006:11:21:10:27:00:SJ cbx_lpm_divide 2007:01:30:03:58:02:SJ cbx_lpm_mux 2006:11:21:10:27:10:SJ cbx_mgl 2007:04:03:14:06:46:SJ cbx_stratix 2007:04:12:16:43:52:SJ cbx_stratixii 2007:02:12:17:08:26:SJ cbx_stratixiii 2007:03:13:14:47:12:SJ cbx_util_mgl 2007:01:15:12:22:48:SJ VERSION_END
--altsrt_div CBX_AUTO_BLACKBOX="ALL" DECODER_SUPPORT="NO" DEVICE_FAMILY="Cyclone II" INIT_FILE="div.hex" ITERATION=14 PIPELINE=32 WIDTH_DIV=24 aclr clock denom divider numer quotient remain
--VERSION_BEGIN 7.1 cbx_altbarrel_shift 2006:08:31:00:41:52:SJ cbx_altfp_div 2007:03:01:19:17:12:SJ cbx_altsyncram 2007:03:22:08:29:24:SJ cbx_cycloneii 2007:01:23:09:39:40:SJ cbx_lpm_abs 2006:04:25:14:52:42:SJ cbx_lpm_add_sub 2007:01:08:11:15:18:SJ cbx_lpm_compare 2007:02:05:11:33:54:SJ cbx_lpm_decode 2006:11:21:10:27:00:SJ cbx_lpm_divide 2007:01:30:03:58:02:SJ cbx_lpm_mux 2006:11:21:10:27:10:SJ cbx_mgl 2007:04:03:14:06:46:SJ cbx_stratix 2007:04:12:16:43:52:SJ cbx_stratixii 2007:02:12:17:08:26:SJ cbx_stratixiii 2007:03:13:14:47:12:SJ cbx_util_mgl 2007:01:15:12:22:48:SJ VERSION_END
--adder_block CBX_AUTO_BLACKBOX="ALL" WIDTH_DIV=24 adder_var divider_next divider_reg neg_qkd_reg Rk_next Rk_reg
--VERSION_BEGIN 7.1 cbx_altbarrel_shift 2006:08:31:00:41:52:SJ cbx_altfp_div 2007:03:01:19:17:12:SJ cbx_altsyncram 2007:03:22:08:29:24:SJ cbx_cycloneii 2007:01:23:09:39:40:SJ cbx_lpm_abs 2006:04:25:14:52:42:SJ cbx_lpm_add_sub 2007:01:08:11:15:18:SJ cbx_lpm_compare 2007:02:05:11:33:54:SJ cbx_lpm_decode 2006:11:21:10:27:00:SJ cbx_lpm_divide 2007:01:30:03:58:02:SJ cbx_lpm_mux 2006:11:21:10:27:10:SJ cbx_mgl 2007:04:03:14:06:46:SJ cbx_stratix 2007:04:12:16:43:52:SJ cbx_stratixii 2007:02:12:17:08:26:SJ cbx_stratixiii 2007:03:13:14:47:12:SJ cbx_util_mgl 2007:01:15:12:22:48:SJ VERSION_END
LIBRARY lpm;
USE lpm.all;
--synthesis_resources = lpm_add_sub 1
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY div_adder_block_vca IS
PORT
(
adder_var : IN STD_LOGIC;
divider_next : OUT STD_LOGIC_VECTOR (23 DOWNTO 0);
divider_reg : IN STD_LOGIC_VECTOR (23 DOWNTO 0);
neg_qkd_reg : IN STD_LOGIC_VECTOR (26 DOWNTO 0);
Rk_next : OUT STD_LOGIC_VECTOR (24 DOWNTO 0);
Rk_reg : IN STD_LOGIC_VECTOR (24 DOWNTO 0)
);
END div_adder_block_vca;
ARCHITECTURE RTL OF div_adder_block_vca IS
ATTRIBUTE synthesis_clearbox : boolean;
ATTRIBUTE synthesis_clearbox OF RTL : ARCHITECTURE IS true;
SIGNAL wire_add_sub38_result : STD_LOGIC_VECTOR (26 DOWNTO 0);
SIGNAL divider_next_1a_w : STD_LOGIC_VECTOR (23 DOWNTO 0);
SIGNAL padded_2_zeros_w : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL Rk_adder_padded_lsb_w : STD_LOGIC_VECTOR (26 DOWNTO 0);
SIGNAL Rk_next_1a_w : STD_LOGIC_VECTOR (24 DOWNTO 0);
COMPONENT lpm_add_sub
GENERIC
(
LPM_DIRECTION : STRING := "DEFAULT";
LPM_PIPELINE : NATURAL := 0;
LPM_REPRESENTATION : STRING := "SIGNED";
LPM_WIDTH : NATURAL;
lpm_hint : STRING := "UNUSED";
lpm_type : STRING := "lpm_add_sub"
);
PORT
(
aclr : IN STD_LOGIC := '0';
add_sub : IN STD_LOGIC := '1';
cin : IN STD_LOGIC := 'Z';
clken : IN STD_LOGIC := '1';
clock : IN STD_LOGIC := '0';
cout : OUT STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR(LPM_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
datab : IN STD_LOGIC_VECTOR(LPM_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
overflow : OUT STD_LOGIC;
result : OUT STD_LOGIC_VECTOR(LPM_WIDTH-1 DOWNTO 0)
);
END COMPONENT;
BEGIN
divider_next <= divider_next_1a_w;
divider_next_1a_w <= divider_reg;
padded_2_zeros_w <= "00";
Rk_adder_padded_lsb_w <= ( Rk_reg & padded_2_zeros_w);
Rk_next <= Rk_next_1a_w;
Rk_next_1a_w <= wire_add_sub38_result(24 DOWNTO 0);
add_sub38 : lpm_add_sub
GENERIC MAP (
LPM_WIDTH => 27,
lpm_hint => "ONE_INPUT_IS_CONSTANT=NO"
)
PORT MAP (
add_sub => adder_var,
dataa => Rk_adder_padded_lsb_w,
datab => neg_qkd_reg,
result => wire_add_sub38_result
);
END RTL; --div_adder_block_vca
--adder_last_block CBX_AUTO_BLACKBOX="ALL" WIDTH_DIV=24 adder_var divider_next divider_reg neg_qkd_reg Rk_next Rk_reg
--VERSION_BEGIN 7.1 cbx_altbarrel_shift 2006:08:31:00:41:52:SJ cbx_altfp_div 2007:03:01:19:17:12:SJ cbx_altsyncram 2007:03:22:08:29:24:SJ cbx_cycloneii 2007:01:23:09:39:40:SJ cbx_lpm_abs 2006:04:25:14:52:42:SJ cbx_lpm_add_sub 2007:01:08:11:15:18:SJ cbx_lpm_compare 2007:02:05:11:33:54:SJ cbx_lpm_decode 2006:11:21:10:27:00:SJ cbx_lpm_divide 2007:01:30:03:58:02:SJ cbx_lpm_mux 2006:11:21:10:27:10:SJ cbx_mgl 2007:04:03:14:06:46:SJ cbx_stratix 2007:04:12:16:43:52:SJ cbx_stratixii 2007:02:12:17:08:26:SJ cbx_stratixiii 2007:03:13:14:47:12:SJ cbx_util_mgl 2007:01:15:12:22:48:SJ VERSION_END
LIBRARY lpm;
USE lpm.all;
--synthesis_resources = lpm_add_sub 1
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY div_adder_last_block_ita IS
PORT
(
adder_var : IN STD_LOGIC;
divider_next : OUT STD_LOGIC_VECTOR (23 DOWNTO 0);
divider_reg : IN STD_LOGIC_VECTOR (23 DOWNTO 0);
neg_qkd_reg : IN STD_LOGIC_VECTOR (26 DOWNTO 0);
Rk_next : OUT STD_LOGIC_VECTOR (26 DOWNTO 0);
Rk_reg : IN STD_LOGIC_VECTOR (24 DOWNTO 0)
);
END div_adder_last_block_ita;
ARCHITECTURE RTL OF div_adder_last_block_ita IS
ATTRIBUTE synthesis_clearbox : boolean;
ATTRIBUTE synthesis_clearbox OF RTL : ARCHITECTURE IS true;
SIGNAL wire_add_sub39_result : STD_LOGIC_VECTOR (26 DOWNTO 0);
SIGNAL divider_next_1a_w : STD_LOGIC_VECTOR (23 DOWNTO 0);
SIGNAL padded_2_zeros_w : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL Rk_adder_padded_lsb_w : STD_LOGIC_VECTOR (26 DOWNTO 0);
SIGNAL true_Rk_1a_w : STD_LOGIC_VECTOR (26 DOWNTO 0);
COMPONENT lpm_add_sub
GENERIC
(
LPM_DIRECTION : STRING := "DEFAULT";
LPM_PIPELINE : NATURAL := 0;
LPM_REPRESENTATION : STRING := "SIGNED";
LPM_WIDTH : NATURAL;
lpm_hint : STRING := "UNUSED";
lpm_type : STRING := "lpm_add_sub"
);
PORT
(
aclr : IN STD_LOGIC := '0';
add_sub : IN STD_LOGIC := '1';
cin : IN STD_LOGIC := 'Z';
clken : IN STD_LOGIC := '1';
clock : IN STD_LOGIC := '0';
cout : OUT STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR(LPM_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
datab : IN STD_LOGIC_VECTOR(LPM_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
overflow : OUT STD_LOGIC;
result : OUT STD_LOGIC_VECTOR(LPM_WIDTH-1 DOWNTO 0)
);
END COMPONENT;
BEGIN
divider_next <= divider_next_1a_w;
divider_next_1a_w <= divider_reg;
padded_2_zeros_w <= "00";
Rk_adder_padded_lsb_w <= ( Rk_reg & padded_2_zeros_w);
Rk_next <= true_Rk_1a_w;
true_Rk_1a_w <= wire_add_sub39_result;
add_sub39 : lpm_add_sub
GENERIC MAP (
LPM_WIDTH => 27,
lpm_hint => "ONE_INPUT_IS_CONSTANT=NO"
)
PORT MAP (
add_sub => adder_var,
dataa => Rk_adder_padded_lsb_w,
datab => neg_qkd_reg,
result => wire_add_sub39_result
);
END RTL; --div_adder_last_block_ita
--rom_block CBX_AUTO_BLACKBOX="ALL" DECODER_SUPPORT="NO" DEVICE_FAMILY="Cyclone II" INIT_FILE="div.hex" PIPELINE=2 WIDTH_DIV=24 WIDTH_ROM=3 WIDTH_ROM_ADD=12 aclr adder_var clock divider divider_reg neg_qkd_reg Rk Rk_reg rom
--VERSION_BEGIN 7.1 cbx_altbarrel_shift 2006:08:31:00:41:52:SJ cbx_altfp_div 2007:03:01:19:17:12:SJ cbx_altsyncram 2007:03:22:08:29:24:SJ cbx_cycloneii 2007:01:23:09:39:40:SJ cbx_lpm_abs 2006:04:25:14:52:42:SJ cbx_lpm_add_sub 2007:01:08:11:15:18:SJ cbx_lpm_compare 2007:02:05:11:33:54:SJ cbx_lpm_decode 2006:11:21:10:27:00:SJ cbx_lpm_divide 2007:01:30:03:58:02:SJ cbx_lpm_mux 2006:11:21:10:27:10:SJ cbx_mgl 2007:04:03:14:06:46:SJ cbx_stratix 2007:04:12:16:43:52:SJ cbx_stratixii 2007:02:12:17:08:26:SJ cbx_stratixiii 2007:03:13:14:47:12:SJ cbx_util_mgl 2007:01:15:12:22:48:SJ VERSION_END
LIBRARY altera_mf;
USE altera_mf.all;
--synthesis_resources = altsyncram 1 reg 129
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY div_rom_block_f8k IS
PORT
(
aclr : IN STD_LOGIC := '0';
adder_var : OUT STD_LOGIC;
clock : IN STD_LOGIC := '0';
divider : IN STD_LOGIC_VECTOR (23 DOWNTO 0);
divider_reg : OUT STD_LOGIC_VECTOR (23 DOWNTO 0);
neg_qkd_reg : OUT STD_LOGIC_VECTOR (26 DOWNTO 0);
Rk : IN STD_LOGIC_VECTOR (24 DOWNTO 0);
Rk_reg : OUT STD_LOGIC_VECTOR (24 DOWNTO 0);
rom : OUT STD_LOGIC_VECTOR (2 DOWNTO 0)
);
END div_rom_block_f8k;
ARCHITECTURE RTL OF div_rom_block_f8k IS
ATTRIBUTE synthesis_clearbox : boolean;
ATTRIBUTE synthesis_clearbox OF RTL : ARCHITECTURE IS true;
SIGNAL wire_altsyncram40_q_a : STD_LOGIC_VECTOR (2 DOWNTO 0);
SIGNAL adder_var_dffe : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL divider_dffe_1a : STD_LOGIC_VECTOR(23 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL divider_dffe_2a : STD_LOGIC_VECTOR(23 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL neg_qkd_dffe : STD_LOGIC_VECTOR(26 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL Rk_dffe_1a : STD_LOGIC_VECTOR(24 DOWNTO 0)
-- synopsys translate_off
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