edge.v

检测上升沿的verilog程序

 module edge_detection (
   input  clk,
   input  rst_n,
   input  i_data_in,
   output o_rising_edge
 );
 
 reg r_data_in0;
 //reg r_data_in1;
 
  always@(posedge clk or negedge rst_n) begin
    if(rst_n==1'b0)
        begin
            r_data_in0<=1'b0;
        end
    else 
        begin
            r_data_in0<=i_data_in;
        end
  end

/*  always@(posedge clk or negedge rst_n) begin
    if(rst_n==1'b0)
        begin
            r_data_in1<=1'b0;
        end
    else 
        begin
            r_data_in1<=r_data_in0;
        end
  end   */
  
  assign o_rising_edge=(~r_data_in0)&i_data_in;
    
 endmodule