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📄 wb_rtc.v

📁 // -*- Mode: Verilog -*- // Filename : wb_master.v // Description : Wishbone Master Behavorial //
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	if (fredcnt_sel && wb_we_i)
	  begin
	  	fred_cnt <= wb_dat_i;	
	  end
	else  	
//////////////////////////////////////////////////////////////////////
//
//  	Frequency Division Logic
//

	if (fred_full)
	  begin
		fred_cnt <= 32'b1;
			  
//////////////////////////////////////////////////////////////////////
//
//  	Second Generate Logic
//

	  	if ((bcdsec[3:0] == 4'h9) && (bcdsec[6:4] == 3'h5))
		   begin
		  	 bcdsec[3:0] <= 4'h0;
		  	 bcdsec[6:4] <= 3'h0;
				  
///////////////////////////////////////////////////////////////////////
//
//	Minute Generate Logic
//

		  	if ((bcdmin[3:0] == 4'h9) && (bcdmin[6:4] == 3'h5))
			  begin
		  		bcdmin[3:0] <= 4'h0;
		  		bcdmin[6:4] <= 3'h0;
					  
//////////////////////////////////////////////////////////////////////
//
//	Hour Generate Logic
//

		  		if ((bcdhour[3:0] == 4'h3) && (bcdhour[5:4] == 2'h2))
				  begin
		  			bcdhour[3:0] <= 4'h0;
		  			bcdhour[5:4] <= 2'h0; 

///////////////////////////////////////////////////////////////////////
//
//	Day Generate Logic
//

					if (bcdday == 4'h7)
					  begin
				  		bcdday <= 4'h1;					  				  			
					  end
					else
					  begin
				  		bcdday <= bcdday + 4'h1;
					  end

//
//	Day Generate Logic
//
///////////////////////////////////////////////////////////////////////
	  			
///////////////////////////////////////////////////////////////////////
//
//	Date Generate Logic
//

					if (((bcddate == 6'h29) && (bcdmon == 5'h02) && leapyear) |
		  		   	    ((bcddate == 6'h28) && (bcdmon == 5'h02) && !leapyear) |
		  		  	    ((bcddate == 6'h30) && 
		  		      	    ((bcdmon == 5'h04) | (bcdmon == 5'h06) | (bcdmon == 5'h09) | (bcdmon == 5'h11))) |
		  		   	    ((bcddate == 6'h31) && 
		  		      	    ((bcdmon == 5'h01) | (bcdmon == 5'h03) | (bcdmon == 5'h05) | (bcdmon == 5'h07) | 
		  		       	     (bcdmon == 5'h08) | (bcdmon == 5'h10) | (bcdmon == 5'h12))))
					  begin
					  	bcddate[3:0] <= 4'h1;
					  	bcddate[5:4] <= 2'h0;
			  	
///////////////////////////////////////////////////////////////////////
//
//	Month Generate Logic
//

						if ((bcdmon[4] == 4'h1) && (bcdmon[3:0] == 4'h2))
						  begin
						  	bcdmon[3:0] <= 4'h1;
						  	bcdmon[4] <= !bcdmon[4];
			  	
////////////////////////////////////////////////////////////////////////
//
//	Year Generate Logic
//

							if (bcdyear[11:0] == 12'h999)
							  begin
							  	bcdyear[11:0] <= 12'h0;
							  	bcdyear[15:12] <= bcdyear[15:12] + 4'h1;
							  end
							else
							if ((bcdyear[7:4] == 4'h9) && (bcdyear[3:0] == 4'h9))
							  begin
						  		bcdyear[7:0] <= 8'h0;
						  		bcdyear[11:8] <= bcdyear[11:8] + 4'h1;
							  end
						  	else						 
						    	if (bcdyear[3:0] == 4'h9)
			 		  		  begin
		  						bcdyear[3:0] <= 4'h0;
		  						bcdyear[7:4] <= bcdyear[7:4] + 4'h1;
							    end
							else
							  begin
		  						bcdyear[3:0] <= bcdyear[3:0] + 4'h1;
				 			  end

//
//	Year Generate Logic
//
/////////////////////////////////////////////////////////////////////

						   end
						  else
						  if (bcdmon[3:0] == 4'h9)
			 		  	    begin
		  					bcdmon[3:0] <= 4'h0;
		  					bcdmon[4] <= !bcdmon[4];
						    end
						  else
						    begin
		  					bcdmon[3:0] <= bcdmon[3:0] + 4'h1;
				 		    end

//
//	Month Generate Logic
//						    					  						  	
////////////////////////////////////////////////////////////////////

					  end
					else
					if (bcddate[3:0] == 4'h9)
			 		  begin
		  				bcddate[3:0] <= 4'h0;
		  				bcddate[5:4] <= bcddate[5:4] + 2'h1;
					  end
					else
					  begin
		  				bcddate[3:0] <= bcddate[3:0] + 4'h1;
				 	  end

//
//	Date Generate Logic
//
////////////////////////////////////////////////////////////////////

			  	  end
				else
				if (bcdhour[3:0] == 4'h9)
			 	  begin
		  			bcdhour[3:0] <= 4'h0;
		  			bcdhour[5:4] <= bcdhour[5:4] + 2'h1;
				  end
				else
				  begin
		  			bcdhour[3:0] <= bcdhour[3:0] + 4'h1;
				  end

//
//	Hour Generate Logic
//				  
//////////////////////////////////////////////////////////////////

			  end
			else
			if (bcdmin[3:0] == 4'h9)
			  begin
		  		bcdmin[3:0] <= 4'h0;
		  		bcdmin[6:4] <= bcdmin[6:4] + 3'h1;
			  end
			else
			  begin
		  		bcdmin[3:0] <= bcdmin[3:0] + 4'h1;
			  end

//
//	Minute Generate Logic
//			  		
//////////////////////////////////////////////////////////////////

		  end	
		else
		if (bcdsec[3:0] == 4'h9)
		  begin
		  	bcdsec[3:0] <= 4'h0;
		  	bcdsec[6:4] <= bcdsec[6:4] + 3'h1;
		  end
		else
		  begin
		  	bcdsec[3:0] <= bcdsec[3:0] + 4'h1;
		  end

//
//	Second Generate Logic
//
//////////////////////////////////////////////////////////////////
		  
	end
	else
	   begin
		fred_cnt <= fred_cnt + 32'b1;
	  end

//
//  	Frequency Division Logic
//
///////////////////////////////////////////////////////////////////

  end


assign	fred_full = rtc_con[1] ? (fred_cnt == 32'h1) : (fred_cnt == inicount);


//
// Whether is leap year or not
//
always	@(bcdyear)
  begin
	if (bcdyear[9:0] == 10'h0)
	  begin
	  	leapyear = 1'b1;
	  end
	else
	if (bcdyear[7:0] == 8'h0)
	  begin
	  	leapyear = 1'b0;
	  end
	else
	if (bcdyear[1:0] == 2'b00)
	  begin
	  	leapyear = 1'b1;
	  end
	else
	  begin
	  	leapyear = 1'b0;
	  end
  end


//////////////////////////////////////////////////////////////
//
//	RTC Interrupt Request Generate Logic
//

// Generate interrupt request per second	
always	@(posedge wb_clk_i)
  begin	
	if (rtc_inte[0] && fred_full)
	  begin
		sec_int <= 1'b1;
	  end
	else
	  begin
		sec_int <= 1'b0;
	  end
  end

// Generate interrupt request per minute	  
always	@(posedge wb_clk_i)
  begin	
	if (rtc_inte[1] && bcdsec == 7'h0)
	  begin
		min_int <= 1'b1;
	  end
	else
	  begin
		min_int <= 1'b0;
	  end
  end

// Generate interrupt request per hour
always	@(posedge wb_clk_i)
  begin
	if (rtc_inte[2] && bcdmin == 7'h0)
	  begin
		hour_int <= 1'b1;
	  end
	else
	  begin
		hour_int <= 1'b0;
	  end
  end
	  
// Generate interrupt request per day
always	@(posedge wb_clk_i)
  begin
	if (rtc_inte[3] && bcdhour == 6'h0)
	  begin
		date_int <= 1'b1;
	  end
	else
	  begin
		date_int <= 1'b0;
	  end
  end

// Generate interrupt request per week
always	@(posedge wb_clk_i)
  begin
	if (rtc_inte[4] && bcdday == 4'h1)
	  begin
		week_int <= 1'b1;
	  end
	else
	  begin
		week_int <= 1'b0;
	  end
  end

// Generate interrupt request per month
always	@(posedge wb_clk_i)
  begin
	if (rtc_inte[5] && bcddate == 6'h1)
	  begin
		mon_int <= 1'b1;
	  end
	else
	  begin
		mon_int <= 1'b0;
	  end
  end



//
//	predetermine
//

// Whether the year equals predetermining year 
always	@(posedge wb_clk_i)
  begin  	
	if (int_mask[6])
	  begin
		if (bcdyear == preyear)
		  begin
			equyear <= 1'b1;
		  end
		else
		  begin
			equyear <= 1'b0;
		  end
	  end
	else
	  begin
		equyear <= 1'b1;
	  end
  end
				
// Whether the month equals predetermining month
always	@(posedge wb_clk_i)
  begin
	if (int_mask[5])
	  begin
		if (bcdmon == premon)
		  begin
		  	equmon <= 1'b1;
		  end
		else
		  begin
		  	equmon <= 1'b0;
		  end
	  end
	else
	  begin
		equmon <= 1'b1;
	  end
  end
		
// Whether the date equals predetermining date
always	@(posedge wb_clk_i)
  begin
	if (int_mask[4])
	  begin
		if (bcddate == predate)
		  begin
		  	equdate <= 1'b1;
		  end
		else
		  begin
		  	equdate <= 1'b0;
		  end
	  end
	else
	  begin
		equdate <= 1'b1;
	  end
  end
		
// Whether the day equals predetermining day
always	@(posedge wb_clk_i)
  begin
	if (int_mask[3])
	  begin
		if (bcdday == preday)
		  begin
		  	equday <= 1'b1;
		  end
		else
		  begin
		  	equday <= 1'b0;
		  end
	  end
	else
	  begin
		equday <= 1'b1;
	  end
  end
		  	
// Whether the hour equals predetermining hour
always	@(posedge wb_clk_i)
  begin
	if (int_mask[2])
	  begin 
		if (bcdhour == prehour)
		  begin
			equhour <= 1'b1;
		  end
		else
		  begin
		  	equhour <= 1'b0;
		  end
	  end
	else
	  begin
		equhour <= 1'b1;
	  end
  end
		  
// Whether the minute equals predetermining minute
always	@(posedge wb_clk_i)
  begin
	if (int_mask[1])
	  begin  
		if (bcdmin == premin)
		  begin
		  	equmin <= 1'b1;
		  end
		else
		  begin
		  	equmin <= 1'b0;
		  end
	  end
	else
	  begin
		equmin <= 1'b1;
	  end
  end
		  
// Whether the second equals predetermining second
always	@(posedge wb_clk_i)
  begin		  
	if (int_mask[0])
	  begin
		if (bcdsec == presec) 
		  begin
		  	equsec <= 1'b1;
		  end
		else
		  begin
		  	equsec <= 1'b0;
		  end
	  end
	else
	  begin
		  equsec <= 1'b1;
	  end
  end

assign	equ_int = rtc_inte[6] ? equyear & equmon & equdate & equday & equhour & equmin & equsec : 1'b0;


//
//	RTC Interrupt Request
//

always	@(posedge wb_clk_i or posedge wb_rst_i)
  begin
  	if (wb_rst_i)
  	  begin
  	  	rtc_int <= 1'b0;
  	  end
  	else
  	  begin
  	  	rtc_int <= rtc_int_r;
  	  end
  end

assign	rtc_int_o = rtc_con[6] ? rtc_int : 1'b0;
  
always	@(equ_int or sec_int or min_int or hour_int or
	  date_int or week_int or mon_int or rtc_con)
  begin
  	case (rtc_con[4:2])
  	  3'h0:
  	    begin
  		rtc_int_r = equ_int;	  	
  	    end
  	  3'h1:
  	    begin
  	    	rtc_int_r = sec_int;
  	    end
  	  3'h2:
  	    begin
  	    	rtc_int_r = min_int;
  	    end
  	  3'h3:
  	    begin
  	    	rtc_int_r = hour_int;
  	    end
  	  3'h4:
  	    begin
  	    	rtc_int_r = date_int;
  	    end
  	  3'h5:
  	    begin
  	    	rtc_int_r = week_int;
  	    end
  	  3'h6:
  	    begin
  	    	rtc_int_r = mon_int;
  	    end
  	  3'h7:
  	    begin
  	    	rtc_int_r = 1'b0;
  	    end
  	endcase
  end


endmodule



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