testlatch.map.qmsg

用verilog编写的USB下载线程序 实现USB协议和JTAG接口的数据转换实现状态机。

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 4.2 Build 157 12/07/2004 SJ Full Version " "Info: Version 4.2 Build 157 12/07/2004 SJ Full Version" {  } {  } 0} { "Info" "IQEXE_START_BANNER_TIME" "Tue Dec 13 17:38:10 2005 " "Info: Processing started: Tue Dec 13 17:38:10 2005" {  } {  } 0}  } {  } 4}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --import_settings_files=on --export_settings_files=off testlatch -c testlatch " "Info: Command: quartus_map --import_settings_files=on --export_settings_files=off testlatch -c testlatch" {  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "testlatch.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file testlatch.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 testlatch " "Info: Found entity 1: testlatch" {  } { { "testlatch.bdf" "" { Schematic "D:/RONTEC/POWER/PCI/Altera/testlatch.bdf" { } } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "JtagCore.V 2 2 " "Info: Found 2 design units, including 2 entities, in source file JtagCore.V" { { "Info" "ISGN_ENTITY_NAME" "1 shiftout " "Info: Found entity 1: shiftout" {  } { { "shiftout.v" "" { Text "D:/RONTEC/POWER/PCI/Altera/shiftout.v" 7 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "2 JTAGcore " "Info: Found entity 2: JTAGcore" {  } { { "JtagCore.V" "" { Text "D:/RONTEC/POWER/PCI/Altera/JtagCore.V" 15 -1 0 } }  } 0}  } {  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 6 JtagCore.V(213) " "Warning: Verilog HDL assignment warning at JtagCore.V(213): truncated value with size 32 to match size of target (6)" {  } { { "JtagCore.V" "" { Text "D:/RONTEC/POWER/PCI/Altera/JtagCore.V" 213 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 6 JtagCore.V(218) " "Warning: Verilog HDL assignment warning at JtagCore.V(218): truncated value with size 32 to match size of target (6)" {  } { { "JtagCore.V" "" { Text "D:/RONTEC/POWER/PCI/Altera/JtagCore.V" 218 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 shiftout.v(48) " "Warning: Verilog HDL assignment warning at shiftout.v(48): truncated value with size 32 to match size of target (4)" {  } { { "shiftout.v" "" { Text "D:/RONTEC/POWER/PCI/Altera/shiftout.v" 48 0 0 } }  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "e:/altera/quartus42/libraries/megafunctions/lpm_add_sub.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file e:/altera/quartus42/libraries/megafunctions/lpm_add_sub.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_add_sub " "Info: Found entity 1: lpm_add_sub" {  } { { "lpm_add_sub.tdf" "" { Text "e:/altera/quartus42/libraries/megafunctions/lpm_add_sub.tdf" 106 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "e:/altera/quartus42/libraries/megafunctions/addcore.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file e:/altera/quartus42/libraries/megafunctions/addcore.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 addcore " "Info: Found entity 1: addcore" {  } { { "addcore.tdf" "" { Text "e:/altera/quartus42/libraries/megafunctions/addcore.tdf" 73 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "e:/altera/quartus42/libraries/megafunctions/a_csnbuffer.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file e:/altera/quartus42/libraries/megafunctions/a_csnbuffer.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 a_csnbuffer " "Info: Found entity 1: a_csnbuffer" {  } { { "a_csnbuffer.tdf" "" { Text "e:/altera/quartus42/libraries/megafunctions/a_csnbuffer.tdf" 10 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "e:/altera/quartus42/libraries/megafunctions/altshift.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file e:/altera/quartus42/libraries/megafunctions/altshift.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altshift " "Info: Found entity 1: altshift" {  } { { "altshift.tdf" "" { Text "e:/altera/quartus42/libraries/megafunctions/altshift.tdf" 34 1 0 } }  } 0}  } {  } 0}
{ "Info" "IOPT_SMP_MACHINE_PREPROCESS_STAT" "\|testlatch\|JTAGcore:inst4\|SM 8 0 " "Info: State machine \"\|testlatch\|JTAGcore:inst4\|SM\" contains 8 states and 0 state bits" {  } {  } 0}
{ "Info" "IOPT_SMP_MACHINE_REPORT_PROCESSOR" "Auto \|testlatch\|JTAGcore:inst4\|SM " "Info: Selected Auto state machine encoding method for state machine \"\|testlatch\|JTAGcore:inst4\|SM\"" {  } {  } 0}
{ "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_HEADER" "\|testlatch\|JTAGcore:inst4\|SM " "Info: Encoding result for state machine \"\|testlatch\|JTAGcore:inst4\|SM\"" { { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS_HEADER" "3 " "Info: Completed encoding using 3 state bits" { { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "JTAGcore:inst4\|SM~127 " "Info: Encoded state bit \"JTAGcore:inst4\|SM~127\"" {  } {  } 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "JTAGcore:inst4\|SM~126 " "Info: Encoded state bit \"JTAGcore:inst4\|SM~126\"" {  } {  } 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "JTAGcore:inst4\|SM~125 " "Info: Encoded state bit \"JTAGcore:inst4\|SM~125\"" {  } {  } 0}  } {  } 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|testlatch\|JTAGcore:inst4\|SM.Idle 000 " "Info: State \"\|testlatch\|JTAGcore:inst4\|SM.Idle\" uses code string \"000\"" {  } { { "JtagCore.V" "" { Text "D:/RONTEC/POWER/PCI/Altera/JtagCore.V" 52 -1 0 } }  } 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|testlatch\|JTAGcore:inst4\|SM.ReadString2 110 " "Info: State \"\|testlatch\|JTAGcore:inst4\|SM.ReadString2\" uses code string \"110\"" {  } { { "JtagCore.V" "" { Text "D:/RONTEC/POWER/PCI/Altera/JtagCore.V" 52 -1 0 } }  } 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|testlatch\|JTAGcore:inst4\|SM.WR_End 111 " "Info: State \"\|testlatch\|JTAGcore:inst4\|SM.WR_End\" uses code string \"111\"" {  } { { "JtagCore.V" "" { Text "D:/RONTEC/POWER/PCI/Altera/JtagCore.V" 52 -1 0 } }  } 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|testlatch\|JTAGcore:inst4\|SM.WR_Active 100 " "Info: State \"\|testlatch\|JTAGcore:inst4\|SM.WR_Active\" uses code string \"100\"" {  } { { "JtagCore.V" "" { Text "D:/RONTEC/POWER/PCI/Altera/JtagCore.V" 52 -1 0 } }  } 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|testlatch\|JTAGcore:inst4\|SM.RD_Active 010 " "Info: State \"\|testlatch\|JTAGcore:inst4\|SM.RD_Active\" uses code string \"010\"" {  } { { "JtagCore.V" "" { Text "D:/RONTEC/POWER/PCI/Altera/JtagCore.V" 52 -1 0 } }  } 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|testlatch\|JTAGcore:inst4\|SM.ReadString 011 " "Info: State \"\|testlatch\|JTAGcore:inst4\|SM.ReadString\" uses code string \"011\"" {  } { { "JtagCore.V" "" { Text "D:/RONTEC/POWER/PCI/Altera/JtagCore.V" 52 -1 0 } }  } 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|testlatch\|JTAGcore:inst4\|SM.Parcer 001 " "Info: State \"\|testlatch\|JTAGcore:inst4\|SM.Parcer\" uses code string \"001\"" {  } { { "JtagCore.V" "" { Text "D:/RONTEC/POWER/PCI/Altera/JtagCore.V" 52 -1 0 } }  } 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|testlatch\|JTAGcore:inst4\|SM.ReadString3 101 " "Info: State \"\|testlatch\|JTAGcore:inst4\|SM.ReadString3\" uses code string \"101\"" {  } { { "JtagCore.V" "" { Text "D:/RONTEC/POWER/PCI/Altera/JtagCore.V" 52 -1 0 } }  } 0}  } {  } 0}
{ "Info" "IOPT_MLS_IGNORED_SUMMARY" "7 " "Info: Ignored 7 buffer(s)" { { "Info" "IOPT_MLS_IGNORED_SOFT" "7 " "Info: Ignored 7 SOFT buffer(s)" {  } {  } 0}  } {  } 0}
{ "Info" "IOPT_MLS_PRESET_POWER_UP" "" "Info: Registers with preset signals will power-up high" {  } { { "JtagCore.V" "" { Text "D:/RONTEC/POWER/PCI/Altera/JtagCore.V" 27 -1 0 } } { "JtagCore.V" "" { Text "D:/RONTEC/POWER/PCI/Altera/JtagCore.V" 31 -1 0 } } { "JtagCore.V" "" { Text "D:/RONTEC/POWER/PCI/Altera/JtagCore.V" 102 -1 0 } } { "JtagCore.V" "" { Text "D:/RONTEC/POWER/PCI/Altera/JtagCore.V" 31 -1 0 } }  } 0}
{ "Info" "IMTM_MTM_PROMOTE_GLOBAL" "" "Info: Promoted pin-driven signal(s) to global signal" { { "Info" "IMTM_MTM_PROMOTE_GLOBAL_CLOCK" "CLK " "Info: Promoted clock signal driven by pin \"CLK\" to global clock signal" {  } {  } 0}  } {  } 0}
{ "Info" "ISCL_SCL_TM_SUMMARY" "71 " "Info: Implemented 71 device resources after synthesis - the final resource count might be different" { { "Info" "ISCL_SCL_TM_IPINS" "10 " "Info: Implemented 10 input pins" {  } {  } 0} { "Info" "ISCL_SCL_TM_OPINS" "10 " "Info: Implemented 10 output pins" {  } {  } 0} { "Info" "ISCL_SCL_TM_BIDIRS" "8 " "Info: Implemented 8 bidirectional pins" {  } {  } 0} { "Info" "ISCL_SCL_TM_MCELLS" "43 " "Info: Implemented 43 macrocells" {  } {  } 0}  } {  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 3 s " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 3 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Tue Dec 13 17:38:22 2005 " "Info: Processing ended: Tue Dec 13 17:38:22 2005" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:13 " "Info: Elapsed time: 00:00:13" {  } {  } 0}  } {  } 0}