📄 testlatch.tan.qmsg

📁 用verilog编写的USB下载线程序实现USB协议和JTAG接口的数据转换实现状态机。
💻 QMSG
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{ "Info" "ITDB_FULL_TCO_RESULT" "CLK D\[0\] JTAGcore:inst4\|direct 14.000 ns register " "Info: tco from clock \"CLK\" to destination pin \"D\[0\]\" through register \"JTAGcore:inst4\|direct\" is 14.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK source 3.600 ns + Longest register " "Info: + Longest clock path from clock \"CLK\" to source register is 3.600 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.300 ns) 2.300 ns CLK 1 CLK PIN_40 34 " "Info: 1: + IC(0.000 ns) + CELL(2.300 ns) = 2.300 ns; Loc. = PIN_40; Fanout = 34; CLK Node = 'CLK'" {  } { { "D:/RONTEC/POWER/PCI/Altera/db/testlatch_cmp.qrpt" "" { Report "D:/RONTEC/POWER/PCI/Altera/db/testlatch_cmp.qrpt" Compiler "testlatch" "UNKNOWN" "V1" "D:/RONTEC/POWER/PCI/Altera/db/testlatch.quartus_db" { Floorplan "D:/RONTEC/POWER/PCI/Altera/" "" "" { CLK } "NODE_NAME" } "" } } { "testlatch.bdf" "" { Schematic "D:/RONTEC/POWER/PCI/Altera/testlatch.bdf" { { 360 -616 -448 376 "CLK" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.300 ns) 3.600 ns JTAGcore:inst4\|direct 2 REG LC50 9 " "Info: 2: + IC(0.000 ns) + CELL(1.300 ns) = 3.600 ns; Loc. = LC50; Fanout = 9; REG Node = 'JTAGcore:inst4\|direct'" {  } { { "D:/RONTEC/POWER/PCI/Altera/db/testlatch_cmp.qrpt" "" { Report "D:/RONTEC/POWER/PCI/Altera/db/testlatch_cmp.qrpt" Compiler "testlatch" "UNKNOWN" "V1" "D:/RONTEC/POWER/PCI/Altera/db/testlatch.quartus_db" { Floorplan "D:/RONTEC/POWER/PCI/Altera/" "" "1.300 ns" { CLK JTAGcore:inst4|direct } "NODE_NAME" } "" } } { "JtagCore.V" "" { Text "D:/RONTEC/POWER/PCI/Altera/JtagCore.V" 102 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.600 ns 100.00 % " "Info: Total cell delay = 3.600 ns ( 100.00 % )" {  } {  } 0}  } { { "D:/RONTEC/POWER/PCI/Altera/db/testlatch_cmp.qrpt" "" { Report "D:/RONTEC/POWER/PCI/Altera/db/testlatch_cmp.qrpt" Compiler "testlatch" "UNKNOWN" "V1" "D:/RONTEC/POWER/PCI/Altera/db/testlatch.quartus_db" { Floorplan "D:/RONTEC/POWER/PCI/Altera/" "" "3.600 ns" { CLK JTAGcore:inst4|direct } "NODE_NAME" } "" } } { "e:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus42/bin/Technology_Viewer.qrui" "3.600 ns" { CLK CLK~out JTAGcore:inst4|direct } { 0.000ns 0.000ns 0.000ns } { 0.000ns 2.300ns 1.300ns } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "1.600 ns + " "Info: + Micro clock to output delay of source is 1.600 ns" {  } { { "JtagCore.V" "" { Text "D:/RONTEC/POWER/PCI/Altera/JtagCore.V" 102 -1 0 } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "8.800 ns + Longest register pin " "Info: + Longest register to pin delay is 8.800 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns JTAGcore:inst4\|direct 1 REG LC50 9 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC50; Fanout = 9; REG Node = 'JTAGcore:inst4\|direct'" {  } { { "D:/RONTEC/POWER/PCI/Altera/db/testlatch_cmp.qrpt" "" { Report "D:/RONTEC/POWER/PCI/Altera/db/testlatch_cmp.qrpt" Compiler "testlatch" "UNKNOWN" "V1" "D:/RONTEC/POWER/PCI/Altera/db/testlatch.quartus_db" { Floorplan "D:/RONTEC/POWER/PCI/Altera/" "" "" { JTAGcore:inst4|direct } "NODE_NAME" } "" } } { "JtagCore.V" "" { Text "D:/RONTEC/POWER/PCI/Altera/JtagCore.V" 102 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.500 ns) + CELL(4.500 ns) 7.000 ns JTAGcore:inst4\|To_FT245\[0\]~16 2 COMB LC5 1 " "Info: 2: + IC(2.500 ns) + CELL(4.500 ns) = 7.000 ns; Loc. = LC5; Fanout = 1; COMB Node = 'JTAGcore:inst4\|To_FT245\[0\]~16'" {  } { { "D:/RONTEC/POWER/PCI/Altera/db/testlatch_cmp.qrpt" "" { Report "D:/RONTEC/POWER/PCI/Altera/db/testlatch_cmp.qrpt" Compiler "testlatch" "UNKNOWN" "V1" "D:/RONTEC/POWER/PCI/Altera/db/testlatch.quartus_db" { Floorplan "D:/RONTEC/POWER/PCI/Altera/" "" "7.000 ns" { JTAGcore:inst4|direct JTAGcore:inst4|To_FT245[0]~16 } "NODE_NAME" } "" } } { "JtagCore.V" "" { Text "D:/RONTEC/POWER/PCI/Altera/JtagCore.V" 43 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.800 ns) 8.800 ns D\[0\] 3 PIN PIN_2 0 " "Info: 3: + IC(0.000 ns) + CELL(1.800 ns) = 8.800 ns; Loc. = PIN_2; Fanout = 0; PIN Node = 'D\[0\]'" {  } { { "D:/RONTEC/POWER/PCI/Altera/db/testlatch_cmp.qrpt" "" { Report "D:/RONTEC/POWER/PCI/Altera/db/testlatch_cmp.qrpt" Compiler "testlatch" "UNKNOWN" "V1" "D:/RONTEC/POWER/PCI/Altera/db/testlatch.quartus_db" { Floorplan "D:/RONTEC/POWER/PCI/Altera/" "" "1.800 ns" { JTAGcore:inst4|To_FT245[0]~16 D[0] } "NODE_NAME" } "" } } { "testlatch.bdf" "" { Schematic "D:/RONTEC/POWER/PCI/Altera/testlatch.bdf" { { 296 -272 -96 312 "D\[7..0\]" "" } } } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "6.300 ns 71.59 % " "Info: Total cell delay = 6.300 ns ( 71.59 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.500 ns 28.41 % " "Info: Total interconnect delay = 2.500 ns ( 28.41 % )" {  } {  } 0}  } { { "D:/RONTEC/POWER/PCI/Altera/db/testlatch_cmp.qrpt" "" { Report "D:/RONTEC/POWER/PCI/Altera/db/testlatch_cmp.qrpt" Compiler "testlatch" "UNKNOWN" "V1" "D:/RONTEC/POWER/PCI/Altera/db/testlatch.quartus_db" { Floorplan "D:/RONTEC/POWER/PCI/Altera/" "" "8.800 ns" { JTAGcore:inst4|direct JTAGcore:inst4|To_FT245[0]~16 D[0] } "NODE_NAME" } "" } } { "e:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus42/bin/Technology_Viewer.qrui" "8.800 ns" { JTAGcore:inst4|direct JTAGcore:inst4|To_FT245[0]~16 D[0] } { 0.000ns 2.500ns 0.000ns } { 0.000ns 4.500ns 1.800ns } } }  } 0}  } { { "D:/RONTEC/POWER/PCI/Altera/db/testlatch_cmp.qrpt" "" { Report "D:/RONTEC/POWER/PCI/Altera/db/testlatch_cmp.qrpt" Compiler "testlatch" "UNKNOWN" "V1" "D:/RONTEC/POWER/PCI/Altera/db/testlatch.quartus_db" { Floorplan "D:/RONTEC/POWER/PCI/Altera/" "" "3.600 ns" { CLK JTAGcore:inst4|direct } "NODE_NAME" } "" } } { "e:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus42/bin/Technology_Viewer.qrui" "3.600 ns" { CLK CLK~out JTAGcore:inst4|direct } { 0.000ns 0.000ns 0.000ns } { 0.000ns 2.300ns 1.300ns } } } { "D:/RONTEC/POWER/PCI/Altera/db/testlatch_cmp.qrpt" "" { Report "D:/RONTEC/POWER/PCI/Altera/db/testlatch_cmp.qrpt" Compiler "testlatch" "UNKNOWN" "V1" "D:/RONTEC/POWER/PCI/Altera/db/testlatch.quartus_db" { Floorplan "D:/RONTEC/POWER/PCI/Altera/" "" "8.800 ns" { JTAGcore:inst4|direct JTAGcore:inst4|To_FT245[0]~16 D[0] } "NODE_NAME" } "" } } { "e:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus42/bin/Technology_Viewer.qrui" "8.800 ns" { JTAGcore:inst4|direct JTAGcore:inst4|To_FT245[0]~16 D[0] } { 0.000ns 2.500ns 0.000ns } { 0.000ns 4.500ns 1.800ns } } }  } 0}
{ "Info" "ITDB_FULL_TPD_RESULT" "CDONE D\[0\] 10.100 ns Longest " "Info: Longest tpd from source pin \"CDONE\" to destination pin \"D\[0\]\" is 10.100 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.400 ns) 1.400 ns CDONE 1 PIN PIN_28 3 " "Info: 1: + IC(0.000 ns) + CELL(1.400 ns) = 1.400 ns; Loc. = PIN_28; Fanout = 3; PIN Node = 'CDONE'" {  } { { "D:/RONTEC/POWER/PCI/Altera/db/testlatch_cmp.qrpt" "" { Report "D:/RONTEC/POWER/PCI/Altera/db/testlatch_cmp.qrpt" Compiler "testlatch" "UNKNOWN" "V1" "D:/RONTEC/POWER/PCI/Altera/db/testlatch.quartus_db" { Floorplan "D:/RONTEC/POWER/PCI/Altera/" "" "" { CDONE } "NODE_NAME" } "" } } { "testlatch.bdf" "" { Schematic "D:/RONTEC/POWER/PCI/Altera/testlatch.bdf" { { 376 -688 -520 392 "CDONE" "" } { 368 -520 -448 384 "CDONE" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.400 ns) + CELL(4.500 ns) 8.300 ns JTAGcore:inst4\|To_FT245\[0\]~16 2 COMB LC5 1 " "Info: 2: + IC(2.400 ns) + CELL(4.500 ns) = 8.300 ns; Loc. = LC5; Fanout = 1; COMB Node = 'JTAGcore:inst4\|To_FT245\[0\]~16'" {  } { { "D:/RONTEC/POWER/PCI/Altera/db/testlatch_cmp.qrpt" "" { Report "D:/RONTEC/POWER/PCI/Altera/db/testlatch_cmp.qrpt" Compiler "testlatch" "UNKNOWN" "V1" "D:/RONTEC/POWER/PCI/Altera/db/testlatch.quartus_db" { Floorplan "D:/RONTEC/POWER/PCI/Altera/" "" "6.900 ns" { CDONE JTAGcore:inst4|To_FT245[0]~16 } "NODE_NAME" } "" } } { "JtagCore.V" "" { Text "D:/RONTEC/POWER/PCI/Altera/JtagCore.V" 43 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.800 ns) 10.100 ns D\[0\] 3 PIN PIN_2 0 " "Info: 3: + IC(0.000 ns) + CELL(1.800 ns) = 10.100 ns; Loc. = PIN_2; Fanout = 0; PIN Node = 'D\[0\]'" {  } { { "D:/RONTEC/POWER/PCI/Altera/db/testlatch_cmp.qrpt" "" { Report "D:/RONTEC/POWER/PCI/Altera/db/testlatch_cmp.qrpt" Compiler "testlatch" "UNKNOWN" "V1" "D:/RONTEC/POWER/PCI/Altera/db/testlatch.quartus_db" { Floorplan "D:/RONTEC/POWER/PCI/Altera/" "" "1.800 ns" { JTAGcore:inst4|To_FT245[0]~16 D[0] } "NODE_NAME" } "" } } { "testlatch.bdf" "" { Schematic "D:/RONTEC/POWER/PCI/Altera/testlatch.bdf" { { 296 -272 -96 312 "D\[7..0\]" "" } } } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "7.700 ns 76.24 % " "Info: Total cell delay = 7.700 ns ( 76.24 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.400 ns 23.76 % " "Info: Total interconnect delay = 2.400 ns ( 23.76 % )" {  } {  } 0}  } { { "D:/RONTEC/POWER/PCI/Altera/db/testlatch_cmp.qrpt" "" { Report "D:/RONTEC/POWER/PCI/Altera/db/testlatch_cmp.qrpt" Compiler "testlatch" "UNKNOWN" "V1" "D:/RONTEC/POWER/PCI/Altera/db/testlatch.quartus_db" { Floorplan "D:/RONTEC/POWER/PCI/Altera/" "" "10.100 ns" { CDONE JTAGcore:inst4|To_FT245[0]~16 D[0] } "NODE_NAME" } "" } } { "e:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus42/bin/Technology_Viewer.qrui" "10.100 ns" { CDONE CDONE~out JTAGcore:inst4|To_FT245[0]~16 D[0] } { 0.000ns 0.000ns 2.400ns 0.000ns } { 0.000ns 1.400ns 4.500ns 1.800ns } } }  } 0}
{ "Info" "ITDB_TH_RESULT" "JTAGcore:inst4\|RED_LED D\[4\] CLK -0.100 ns register " "Info: th for register \"JTAGcore:inst4\|RED_LED\" (data pin = \"D\[4\]\", clock pin = \"CLK\") is -0.100 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK destination 3.600 ns + Longest register " "Info: + Longest clock path from clock \"CLK\" to destination register is 3.600 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.300 ns) 2.300 ns CLK 1 CLK PIN_40 34 " "Info: 1: + IC(0.000 ns) + CELL(2.300 ns) = 2.300 ns; Loc. = PIN_40; Fanout = 34; CLK Node = 'CLK'" {  } { { "D:/RONTEC/POWER/PCI/Altera/db/testlatch_cmp.qrpt" "" { Report "D:/RONTEC/POWER/PCI/Altera/db/testlatch_cmp.qrpt" Compiler "testlatch" "UNKNOWN" "V1" "D:/RONTEC/POWER/PCI/Altera/db/testlatch.quartus_db" { Floorplan "D:/RONTEC/POWER/PCI/Altera/" "" "" { CLK } "NODE_NAME" } "" } } { "testlatch.bdf" "" { Schematic "D:/RONTEC/POWER/PCI/Altera/testlatch.bdf" { { 360 -616 -448 376 "CLK" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.300 ns) 3.600 ns JTAGcore:inst4\|RED_LED 2 REG LC62 4 " "Info: 2: + IC(0.000 ns) + CELL(1.300 ns) = 3.600 ns; Loc. = LC62; Fanout = 4; REG Node = 'JTAGcore:inst4\|RED_LED'" {  } { { "D:/RONTEC/POWER/PCI/Altera/db/testlatch_cmp.qrpt" "" { Report "D:/RONTEC/POWER/PCI/Altera/db/testlatch_cmp.qrpt" Compiler "testlatch" "UNKNOWN" "V1" "D:/RONTEC/POWER/PCI/Altera/db/testlatch.quartus_db" { Floorplan "D:/RONTEC/POWER/PCI/Altera/" "" "1.300 ns" { CLK JTAGcore:inst4|RED_LED } "NODE_NAME" } "" } } { "JtagCore.V" "" { Text "D:/RONTEC/POWER/PCI/Altera/JtagCore.V" 27 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.600 ns 100.00 % " "Info: Total cell delay = 3.600 ns ( 100.00 % )" {  } {  } 0}  } { { "D:/RONTEC/POWER/PCI/Altera/db/testlatch_cmp.qrpt" "" { Report "D:/RONTEC/POWER/PCI/Altera/db/testlatch_cmp.qrpt" Compiler "testlatch" "UNKNOWN" "V1" "D:/RONTEC/POWER/PCI/Altera/db/testlatch.quartus_db" { Floorplan "D:/RONTEC/POWER/PCI/Altera/" "" "3.600 ns" { CLK JTAGcore:inst4|RED_LED } "NODE_NAME" } "" } } { "e:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus42/bin/Technology_Viewer.qrui" "3.600 ns" { CLK CLK~out JTAGcore:inst4|RED_LED } { 0.000ns 0.000ns 0.000ns } { 0.000ns 2.300ns 1.300ns } } }  } 0} { "Info" "ITDB_FULL_TH_DELAY" "1.300 ns + " "Info: + Micro hold delay of destination is 1.300 ns" {  } { { "JtagCore.V" "" { Text "D:/RONTEC/POWER/PCI/Altera/JtagCore.V" 27 -1 0 } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.000 ns - Shortest pin register " "Info: - Shortest pin to register delay is 5.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns D\[4\] 1 PIN PIN_8 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PIN_8; Fanout = 1; PIN Node = 'D\[4\]'" {  } { { "D:/RONTEC/POWER/PCI/Altera/db/testlatch_cmp.qrpt" "" { Report "D:/RONTEC/POWER/PCI/Altera/db/testlatch_cmp.qrpt" Compiler "testlatch" "UNKNOWN" "V1" "D:/RONTEC/POWER/PCI/Altera/db/testlatch.quartus_db" { Floorplan "D:/RONTEC/POWER/PCI/Altera/" "" "" { D[4] } "NODE_NAME" } "" } } { "testlatch.bdf" "" { Schematic "D:/RONTEC/POWER/PCI/Altera/testlatch.bdf" { { 296 -272 -96 312 "D\[7..0\]" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.400 ns) 1.400 ns D~3 2 COMB IO30 8 " "Info: 2: + IC(0.000 ns) + CELL(1.400 ns) = 1.400 ns; Loc. = IO30; Fanout = 8; COMB Node = 'D~3'" {  } { { "D:/RONTEC/POWER/PCI/Altera/db/testlatch_cmp.qrpt" "" { Report "D:/RONTEC/POWER/PCI/Altera/db/testlatch_cmp.qrpt" Compiler "testlatch" "UNKNOWN" "V1" "D:/RONTEC/POWER/PCI/Altera/db/testlatch.quartus_db" { Floorplan "D:/RONTEC/POWER/PCI/Altera/" "" "1.400 ns" { D[4] D~3 } "NODE_NAME" } "" } } { "testlatch.bdf" "" { Schematic "D:/RONTEC/POWER/PCI/Altera/testlatch.bdf" { { 296 -272 -96 312 "D\[7..0\]" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.400 ns) + CELL(1.200 ns) 5.000 ns JTAGcore:inst4\|RED_LED 3 REG LC62 4 " "Info: 3: + IC(2.400 ns) + CELL(1.200 ns) = 5.000 ns; Loc. = LC62; Fanout = 4; REG Node = 'JTAGcore:inst4\|RED_LED'" {  } { { "D:/RONTEC/POWER/PCI/Altera/db/testlatch_cmp.qrpt" "" { Report "D:/RONTEC/POWER/PCI/Altera/db/testlatch_cmp.qrpt" Compiler "testlatch" "UNKNOWN" "V1" "D:/RONTEC/POWER/PCI/Altera/db/testlatch.quartus_db" { Floorplan "D:/RONTEC/POWER/PCI/Altera/" "" "3.600 ns" { D~3 JTAGcore:inst4|RED_LED } "NODE_NAME" } "" } } { "JtagCore.V" "" { Text "D:/RONTEC/POWER/PCI/Altera/JtagCore.V" 27 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.600 ns 52.00 % " "Info: Total cell delay = 2.600 ns ( 52.00 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.400 ns 48.00 % " "Info: Total interconnect delay = 2.400 ns ( 48.00 % )" {  } {  } 0}  } { { "D:/RONTEC/POWER/PCI/Altera/db/testlatch_cmp.qrpt" "" { Report "D:/RONTEC/POWER/PCI/Altera/db/testlatch_cmp.qrpt" Compiler "testlatch" "UNKNOWN" "V1" "D:/RONTEC/POWER/PCI/Altera/db/testlatch.quartus_db" { Floorplan "D:/RONTEC/POWER/PCI/Altera/" "" "5.000 ns" { D[4] D~3 JTAGcore:inst4|RED_LED } "NODE_NAME" } "" } } { "e:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus42/bin/Technology_Viewer.qrui" "5.000 ns" { D[4] D~3 JTAGcore:inst4|RED_LED } { 0.000ns 0.000ns 2.400ns } { 0.000ns 1.400ns 1.200ns } } }  } 0}  } { { "D:/RONTEC/POWER/PCI/Altera/db/testlatch_cmp.qrpt" "" { Report "D:/RONTEC/POWER/PCI/Altera/db/testlatch_cmp.qrpt" Compiler "testlatch" "UNKNOWN" "V1" "D:/RONTEC/POWER/PCI/Altera/db/testlatch.quartus_db" { Floorplan "D:/RONTEC/POWER/PCI/Altera/" "" "3.600 ns" { CLK JTAGcore:inst4|RED_LED } "NODE_NAME" } "" } } { "e:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus42/bin/Technology_Viewer.qrui" "3.600 ns" { CLK CLK~out JTAGcore:inst4|RED_LED } { 0.000ns 0.000ns 0.000ns } { 0.000ns 2.300ns 1.300ns } } } { "D:/RONTEC/POWER/PCI/Altera/db/testlatch_cmp.qrpt" "" { Report "D:/RONTEC/POWER/PCI/Altera/db/testlatch_cmp.qrpt" Compiler "testlatch" "UNKNOWN" "V1" "D:/RONTEC/POWER/PCI/Altera/db/testlatch.quartus_db" { Floorplan "D:/RONTEC/POWER/PCI/Altera/" "" "5.000 ns" { D[4] D~3 JTAGcore:inst4|RED_LED } "NODE_NAME" } "" } } { "e:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus42/bin/Technology_Viewer.qrui" "5.000 ns" { D[4] D~3 JTAGcore:inst4|RED_LED } { 0.000ns 0.000ns 2.400ns } { 0.000ns 1.400ns 1.200ns } } }  } 0}
{ "Info" "ITAN_REQUIREMENTS_MET" "" "Info: All timing requirements were met. See Report window for more details." {  } {  } 0}
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