📄 testlatch.tan.qmsg

📁 用verilog编写的USB下载线程序实现USB协议和JTAG接口的数据转换实现状态机。
💻 QMSG
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{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" {  } {  } 0}
{ "Info" "ITDB_FULL_SLACK_RESULT" "CLK register JTAGcore:inst4\|SM~125 register JTAGcore:inst4\|SM~127 28.9 ns " "Info: Slack time is 28.9 ns for clock \"CLK\" between source register \"JTAGcore:inst4\|SM~125\" and destination register \"JTAGcore:inst4\|SM~127\"" { { "Info" "ITDB_SIMPLE_FMAX_RESULT" "90.09 MHz 11.1 ns " "Info: Fmax is 90.09 MHz (period= 11.1 ns)" {  } {  } 0} { "Info" "ITDB_FULL_P2P_REQUIREMENT_RESULT" "35.500 ns + Largest register register " "Info: + Largest register to register requirement is 35.500 ns" { { "Info" "ITDB_FULL_SETUP_REQUIREMENT" "40.000 ns + " "Info: + Setup relationship between source and destination is 40.000 ns" { { "Info" "ITDB_EDGE_RESULT" "+ Latch 40.000 ns " "Info: + Latch edge is 40.000 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Destination CLK 40.000 ns 0.000 ns  50 " "Info: Clock period of Destination clock \"CLK\" is 40.000 ns with  offset of 0.000 ns and duty cycle of 50" {  } {  } 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Destination Setup 1 " "Info: Multicycle Setup factor for Destination register is 1" {  } {  } 0}  } {  } 0} { "Info" "ITDB_EDGE_RESULT" "- Launch 0.000 ns " "Info: - Launch edge is 0.000 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Source CLK 40.000 ns 0.000 ns  50 " "Info: Clock period of Source clock \"CLK\" is 40.000 ns with  offset of 0.000 ns and duty cycle of 50" {  } {  } 0} { "Info" "ITDB_CLOCK_OFFSET_COMPONENTS" "Source 0.000 ns 0 degrees " "Info: Clock offset from Source is based on specified offset of 0.000 ns and phase shift of 0 degrees of the base clock" {  } {  } 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Source Setup 1 " "Info: Multicycle Setup factor for Source register is 1" {  } {  } 0} { "Info" "ITDB_CLOCK_OFFSET_COMPONENTS" "Destination 0.000 ns 0 degrees " "Info: Clock offset from Destination is based on specified offset of 0.000 ns and phase shift of 0 degrees of the base clock" {  } {  } 0}  } {  } 0} { "Info" "ITDB_SETUP_UNCERTAINTY" "0.000 ns " "Info: Clock setup uncertainty between source and destination is 0.000 ns" {  } {  } 0}  } {  } 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns + Largest " "Info: + Largest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK destination 3.600 ns + Shortest register " "Info: + Shortest clock path from clock \"CLK\" to destination register is 3.600 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.300 ns) 2.300 ns CLK 1 CLK PIN_40 34 " "Info: 1: + IC(0.000 ns) + CELL(2.300 ns) = 2.300 ns; Loc. = PIN_40; Fanout = 34; CLK Node = 'CLK'" {  } { { "D:/RONTEC/POWER/PCI/Altera/db/testlatch_cmp.qrpt" "" { Report "D:/RONTEC/POWER/PCI/Altera/db/testlatch_cmp.qrpt" Compiler "testlatch" "UNKNOWN" "V1" "D:/RONTEC/POWER/PCI/Altera/db/testlatch.quartus_db" { Floorplan "D:/RONTEC/POWER/PCI/Altera/" "" "" { CLK } "NODE_NAME" } "" } } { "testlatch.bdf" "" { Schematic "D:/RONTEC/POWER/PCI/Altera/testlatch.bdf" { { 360 -616 -448 376 "CLK" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.300 ns) 3.600 ns JTAGcore:inst4\|SM~127 2 REG LC28 51 " "Info: 2: + IC(0.000 ns) + CELL(1.300 ns) = 3.600 ns; Loc. = LC28; Fanout = 51; REG Node = 'JTAGcore:inst4\|SM~127'" {  } { { "D:/RONTEC/POWER/PCI/Altera/db/testlatch_cmp.qrpt" "" { Report "D:/RONTEC/POWER/PCI/Altera/db/testlatch_cmp.qrpt" Compiler "testlatch" "UNKNOWN" "V1" "D:/RONTEC/POWER/PCI/Altera/db/testlatch.quartus_db" { Floorplan "D:/RONTEC/POWER/PCI/Altera/" "" "1.300 ns" { CLK JTAGcore:inst4|SM~127 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.600 ns 100.00 % " "Info: Total cell delay = 3.600 ns ( 100.00 % )" {  } {  } 0}  } { { "D:/RONTEC/POWER/PCI/Altera/db/testlatch_cmp.qrpt" "" { Report "D:/RONTEC/POWER/PCI/Altera/db/testlatch_cmp.qrpt" Compiler "testlatch" "UNKNOWN" "V1" "D:/RONTEC/POWER/PCI/Altera/db/testlatch.quartus_db" { Floorplan "D:/RONTEC/POWER/PCI/Altera/" "" "3.600 ns" { CLK JTAGcore:inst4|SM~127 } "NODE_NAME" } "" } } { "e:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus42/bin/Technology_Viewer.qrui" "3.600 ns" { CLK CLK~out JTAGcore:inst4|SM~127 } { 0.000ns 0.000ns 0.000ns } { 0.000ns 2.300ns 1.300ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK source 3.600 ns - Longest register " "Info: - Longest clock path from clock \"CLK\" to source register is 3.600 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.300 ns) 2.300 ns CLK 1 CLK PIN_40 34 " "Info: 1: + IC(0.000 ns) + CELL(2.300 ns) = 2.300 ns; Loc. = PIN_40; Fanout = 34; CLK Node = 'CLK'" {  } { { "D:/RONTEC/POWER/PCI/Altera/db/testlatch_cmp.qrpt" "" { Report "D:/RONTEC/POWER/PCI/Altera/db/testlatch_cmp.qrpt" Compiler "testlatch" "UNKNOWN" "V1" "D:/RONTEC/POWER/PCI/Altera/db/testlatch.quartus_db" { Floorplan "D:/RONTEC/POWER/PCI/Altera/" "" "" { CLK } "NODE_NAME" } "" } } { "testlatch.bdf" "" { Schematic "D:/RONTEC/POWER/PCI/Altera/testlatch.bdf" { { 360 -616 -448 376 "CLK" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.300 ns) 3.600 ns JTAGcore:inst4\|SM~125 2 REG LC32 55 " "Info: 2: + IC(0.000 ns) + CELL(1.300 ns) = 3.600 ns; Loc. = LC32; Fanout = 55; REG Node = 'JTAGcore:inst4\|SM~125'" {  } { { "D:/RONTEC/POWER/PCI/Altera/db/testlatch_cmp.qrpt" "" { Report "D:/RONTEC/POWER/PCI/Altera/db/testlatch_cmp.qrpt" Compiler "testlatch" "UNKNOWN" "V1" "D:/RONTEC/POWER/PCI/Altera/db/testlatch.quartus_db" { Floorplan "D:/RONTEC/POWER/PCI/Altera/" "" "1.300 ns" { CLK JTAGcore:inst4|SM~125 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.600 ns 100.00 % " "Info: Total cell delay = 3.600 ns ( 100.00 % )" {  } {  } 0}  } { { "D:/RONTEC/POWER/PCI/Altera/db/testlatch_cmp.qrpt" "" { Report "D:/RONTEC/POWER/PCI/Altera/db/testlatch_cmp.qrpt" Compiler "testlatch" "UNKNOWN" "V1" "D:/RONTEC/POWER/PCI/Altera/db/testlatch.quartus_db" { Floorplan "D:/RONTEC/POWER/PCI/Altera/" "" "3.600 ns" { CLK JTAGcore:inst4|SM~125 } "NODE_NAME" } "" } } { "e:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus42/bin/Technology_Viewer.qrui" "3.600 ns" { CLK CLK~out JTAGcore:inst4|SM~125 } { 0.000ns 0.000ns 0.000ns } { 0.000ns 2.300ns 1.300ns } } }  } 0}  } { { "D:/RONTEC/POWER/PCI/Altera/db/testlatch_cmp.qrpt" "" { Report "D:/RONTEC/POWER/PCI/Altera/db/testlatch_cmp.qrpt" Compiler "testlatch" "UNKNOWN" "V1" "D:/RONTEC/POWER/PCI/Altera/db/testlatch.quartus_db" { Floorplan "D:/RONTEC/POWER/PCI/Altera/" "" "3.600 ns" { CLK JTAGcore:inst4|SM~127 } "NODE_NAME" } "" } } { "e:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus42/bin/Technology_Viewer.qrui" "3.600 ns" { CLK CLK~out JTAGcore:inst4|SM~127 } { 0.000ns 0.000ns 0.000ns } { 0.000ns 2.300ns 1.300ns } } } { "D:/RONTEC/POWER/PCI/Altera/db/testlatch_cmp.qrpt" "" { Report "D:/RONTEC/POWER/PCI/Altera/db/testlatch_cmp.qrpt" Compiler "testlatch" "UNKNOWN" "V1" "D:/RONTEC/POWER/PCI/Altera/db/testlatch.quartus_db" { Floorplan "D:/RONTEC/POWER/PCI/Altera/" "" "3.600 ns" { CLK JTAGcore:inst4|SM~125 } "NODE_NAME" } "" } } { "e:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus42/bin/Technology_Viewer.qrui" "3.600 ns" { CLK CLK~out JTAGcore:inst4|SM~125 } { 0.000ns 0.000ns 0.000ns } { 0.000ns 2.300ns 1.300ns } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "1.600 ns - " "Info: - Micro clock to output delay of source is 1.600 ns" {  } {  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "2.900 ns - " "Info: - Micro setup delay of destination is 2.900 ns" {  } {  } 0}  } { { "D:/RONTEC/POWER/PCI/Altera/db/testlatch_cmp.qrpt" "" { Report "D:/RONTEC/POWER/PCI/Altera/db/testlatch_cmp.qrpt" Compiler "testlatch" "UNKNOWN" "V1" "D:/RONTEC/POWER/PCI/Altera/db/testlatch.quartus_db" { Floorplan "D:/RONTEC/POWER/PCI/Altera/" "" "3.600 ns" { CLK JTAGcore:inst4|SM~127 } "NODE_NAME" } "" } } { "e:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus42/bin/Technology_Viewer.qrui" "3.600 ns" { CLK CLK~out JTAGcore:inst4|SM~127 } { 0.000ns 0.000ns 0.000ns } { 0.000ns 2.300ns 1.300ns } } } { "D:/RONTEC/POWER/PCI/Altera/db/testlatch_cmp.qrpt" "" { Report "D:/RONTEC/POWER/PCI/Altera/db/testlatch_cmp.qrpt" Compiler "testlatch" "UNKNOWN" "V1" "D:/RONTEC/POWER/PCI/Altera/db/testlatch.quartus_db" { Floorplan "D:/RONTEC/POWER/PCI/Altera/" "" "3.600 ns" { CLK JTAGcore:inst4|SM~125 } "NODE_NAME" } "" } } { "e:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus42/bin/Technology_Viewer.qrui" "3.600 ns" { CLK CLK~out JTAGcore:inst4|SM~125 } { 0.000ns 0.000ns 0.000ns } { 0.000ns 2.300ns 1.300ns } } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.600 ns - Longest register register " "Info: - Longest register to register delay is 6.600 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns JTAGcore:inst4\|SM~125 1 REG LC32 55 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC32; Fanout = 55; REG Node = 'JTAGcore:inst4\|SM~125'" {  } { { "D:/RONTEC/POWER/PCI/Altera/db/testlatch_cmp.qrpt" "" { Report "D:/RONTEC/POWER/PCI/Altera/db/testlatch_cmp.qrpt" Compiler "testlatch" "UNKNOWN" "V1" "D:/RONTEC/POWER/PCI/Altera/db/testlatch.quartus_db" { Floorplan "D:/RONTEC/POWER/PCI/Altera/" "" "" { JTAGcore:inst4|SM~125 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.500 ns) + CELL(1.200 ns) 3.700 ns JTAGcore:inst4\|SM~990 2 COMB LC27 1 " "Info: 2: + IC(2.500 ns) + CELL(1.200 ns) = 3.700 ns; Loc. = LC27; Fanout = 1; COMB Node = 'JTAGcore:inst4\|SM~990'" {  } { { "D:/RONTEC/POWER/PCI/Altera/db/testlatch_cmp.qrpt" "" { Report "D:/RONTEC/POWER/PCI/Altera/db/testlatch_cmp.qrpt" Compiler "testlatch" "UNKNOWN" "V1" "D:/RONTEC/POWER/PCI/Altera/db/testlatch.quartus_db" { Floorplan "D:/RONTEC/POWER/PCI/Altera/" "" "3.700 ns" { JTAGcore:inst4|SM~125 JTAGcore:inst4|SM~990 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.900 ns) 6.600 ns JTAGcore:inst4\|SM~127 3 REG LC28 51 " "Info: 3: + IC(0.000 ns) + CELL(2.900 ns) = 6.600 ns; Loc. = LC28; Fanout = 51; REG Node = 'JTAGcore:inst4\|SM~127'" {  } { { "D:/RONTEC/POWER/PCI/Altera/db/testlatch_cmp.qrpt" "" { Report "D:/RONTEC/POWER/PCI/Altera/db/testlatch_cmp.qrpt" Compiler "testlatch" "UNKNOWN" "V1" "D:/RONTEC/POWER/PCI/Altera/db/testlatch.quartus_db" { Floorplan "D:/RONTEC/POWER/PCI/Altera/" "" "2.900 ns" { JTAGcore:inst4|SM~990 JTAGcore:inst4|SM~127 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.100 ns 62.12 % " "Info: Total cell delay = 4.100 ns ( 62.12 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.500 ns 37.88 % " "Info: Total interconnect delay = 2.500 ns ( 37.88 % )" {  } {  } 0}  } { { "D:/RONTEC/POWER/PCI/Altera/db/testlatch_cmp.qrpt" "" { Report "D:/RONTEC/POWER/PCI/Altera/db/testlatch_cmp.qrpt" Compiler "testlatch" "UNKNOWN" "V1" "D:/RONTEC/POWER/PCI/Altera/db/testlatch.quartus_db" { Floorplan "D:/RONTEC/POWER/PCI/Altera/" "" "6.600 ns" { JTAGcore:inst4|SM~125 JTAGcore:inst4|SM~990 JTAGcore:inst4|SM~127 } "NODE_NAME" } "" } } { "e:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus42/bin/Technology_Viewer.qrui" "6.600 ns" { JTAGcore:inst4|SM~125 JTAGcore:inst4|SM~990 JTAGcore:inst4|SM~127 } { 0.000ns 2.500ns 0.000ns } { 0.000ns 1.200ns 2.900ns } } }  } 0}  } { { "D:/RONTEC/POWER/PCI/Altera/db/testlatch_cmp.qrpt" "" { Report "D:/RONTEC/POWER/PCI/Altera/db/testlatch_cmp.qrpt" Compiler "testlatch" "UNKNOWN" "V1" "D:/RONTEC/POWER/PCI/Altera/db/testlatch.quartus_db" { Floorplan "D:/RONTEC/POWER/PCI/Altera/" "" "3.600 ns" { CLK JTAGcore:inst4|SM~127 } "NODE_NAME" } "" } } { "e:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus42/bin/Technology_Viewer.qrui" "3.600 ns" { CLK CLK~out JTAGcore:inst4|SM~127 } { 0.000ns 0.000ns 0.000ns } { 0.000ns 2.300ns 1.300ns } } } { "D:/RONTEC/POWER/PCI/Altera/db/testlatch_cmp.qrpt" "" { Report "D:/RONTEC/POWER/PCI/Altera/db/testlatch_cmp.qrpt" Compiler "testlatch" "UNKNOWN" "V1" "D:/RONTEC/POWER/PCI/Altera/db/testlatch.quartus_db" { Floorplan "D:/RONTEC/POWER/PCI/Altera/" "" "3.600 ns" { CLK JTAGcore:inst4|SM~125 } "NODE_NAME" } "" } } { "e:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus42/bin/Technology_Viewer.qrui" "3.600 ns" { CLK CLK~out JTAGcore:inst4|SM~125 } { 0.000ns 0.000ns 0.000ns } { 0.000ns 2.300ns 1.300ns } } } { "D:/RONTEC/POWER/PCI/Altera/db/testlatch_cmp.qrpt" "" { Report "D:/RONTEC/POWER/PCI/Altera/db/testlatch_cmp.qrpt" Compiler "testlatch" "UNKNOWN" "V1" "D:/RONTEC/POWER/PCI/Altera/db/testlatch.quartus_db" { Floorplan "D:/RONTEC/POWER/PCI/Altera/" "" "6.600 ns" { JTAGcore:inst4|SM~125 JTAGcore:inst4|SM~990 JTAGcore:inst4|SM~127 } "NODE_NAME" } "" } } { "e:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus42/bin/Technology_Viewer.qrui" "6.600 ns" { JTAGcore:inst4|SM~125 JTAGcore:inst4|SM~990 JTAGcore:inst4|SM~127 } { 0.000ns 2.500ns 0.000ns } { 0.000ns 1.200ns 2.900ns } } }  } 0}
{ "Info" "ITDB_FULL_MIN_SLACK_RESULT" "CLK register JTAGcore:inst4\|SM~126 register JTAGcore:inst4\|direct 4.0 ns " "Info: Minimum slack time is 4.0 ns for clock \"CLK\" between source register \"JTAGcore:inst4\|SM~126\" and destination register \"JTAGcore:inst4\|direct\"" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.700 ns + Shortest register register " "Info: + Shortest register to register delay is 3.700 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns JTAGcore:inst4\|SM~126 1 REG LC23 50 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC23; Fanout = 50; REG Node = 'JTAGcore:inst4\|SM~126'" {  } { { "D:/RONTEC/POWER/PCI/Altera/db/testlatch_cmp.qrpt" "" { Report "D:/RONTEC/POWER/PCI/Altera/db/testlatch_cmp.qrpt" Compiler "testlatch" "UNKNOWN" "V1" "D:/RONTEC/POWER/PCI/Altera/db/testlatch.quartus_db" { Floorplan "D:/RONTEC/POWER/PCI/Altera/" "" "" { JTAGcore:inst4|SM~126 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.500 ns) + CELL(1.200 ns) 3.700 ns JTAGcore:inst4\|direct 2 REG LC50 9 " "Info: 2: + IC(2.500 ns) + CELL(1.200 ns) = 3.700 ns; Loc. = LC50; Fanout = 9; REG Node = 'JTAGcore:inst4\|direct'" {  } { { "D:/RONTEC/POWER/PCI/Altera/db/testlatch_cmp.qrpt" "" { Report "D:/RONTEC/POWER/PCI/Altera/db/testlatch_cmp.qrpt" Compiler "testlatch" "UNKNOWN" "V1" "D:/RONTEC/POWER/PCI/Altera/db/testlatch.quartus_db" { Floorplan "D:/RONTEC/POWER/PCI/Altera/" "" "3.700 ns" { JTAGcore:inst4|SM~126 JTAGcore:inst4|direct } "NODE_NAME" } "" } } { "JtagCore.V" "" { Text "D:/RONTEC/POWER/PCI/Altera/JtagCore.V" 102 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.200 ns 32.43 % " "Info: Total cell delay = 1.200 ns ( 32.43 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.500 ns 67.57 % " "Info: Total interconnect delay = 2.500 ns ( 67.57 % )" {  } {  } 0}  } { { "D:/RONTEC/POWER/PCI/Altera/db/testlatch_cmp.qrpt" "" { Report "D:/RONTEC/POWER/PCI/Altera/db/testlatch_cmp.qrpt" Compiler "testlatch" "UNKNOWN" "V1" "D:/RONTEC/POWER/PCI/Altera/db/testlatch.quartus_db" { Floorplan "D:/RONTEC/POWER/PCI/Altera/" "" "3.700 ns" { JTAGcore:inst4|SM~126 JTAGcore:inst4|direct } "NODE_NAME" } "" } } { "e:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus42/bin/Technology_Viewer.qrui" "3.700 ns" { JTAGcore:inst4|SM~126 JTAGcore:inst4|direct } { 0.0ns 2.5ns } { 0.0ns 1.2ns } } }  } 0} { "Info" "ITDB_FULL_P2P_REQUIREMENT_RESULT" "-0.300 ns - Smallest register register " "Info: - Smallest register to register requirement is -0.300 ns" { { "Info" "ITDB_FULL_HOLD_REQUIREMENT" "0.000 ns + " "Info: + Hold relationship between source and destination is 0.000 ns" { { "Info" "ITDB_EDGE_RESULT" "+ Latch 0.000 ns " "Info: + Latch edge is 0.000 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Destination CLK 40.000 ns 0.000 ns  50 " "Info: Clock period of Destination clock \"CLK\" is 40.000 ns with  offset of 0.000 ns and duty cycle of 50" {  } {  } 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Destination Setup 1 " "Info: Multicycle Setup factor for Destination register is 1" {  } {  } 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Destination Hold 1 " "Info: Multicycle Hold factor for Destination register is 1" {  } {  } 0}  } {  } 0} { "Info" "ITDB_EDGE_RESULT" "- Launch 0.000 ns " "Info: - Launch edge is 0.000 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Source CLK 40.000 ns 0.000 ns  50 " "Info: Clock period of Source clock \"CLK\" is 40.000 ns with  offset of 0.000 ns and duty cycle of 50" {  } {  } 0} { "Info" "ITDB_CLOCK_OFFSET_COMPONENTS" "Source 0.000 ns 0 degrees " "Info: Clock offset from Source is based on specified offset of 0.000 ns and phase shift of 0 degrees of the base clock" {  } {  } 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Source Setup 1 " "Info: Multicycle Setup factor for Source register is 1" {  } {  } 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Source Hold 1 " "Info: Multicycle Hold factor for Source register is 1" {  } {  } 0} { "Info" "ITDB_CLOCK_OFFSET_COMPONENTS" "Destination 0.000 ns 0 degrees " "Info: Clock offset from Destination is based on specified offset of 0.000 ns and phase shift of 0 degrees of the base clock" {  } {  } 0}  } {  } 0} { "Info" "ITDB_HOLD_UNCERTAINTY" "0.000 ns " "Info: Clock hold uncertainty between source and destination is 0.000 ns" {  } {  } 0}  } {  } 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns + Smallest " "Info: + Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK destination 3.600 ns + Longest register " "Info: + Longest clock path from clock \"CLK\" to destination register is 3.600 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.300 ns) 2.300 ns CLK 1 CLK PIN_40 34 " "Info: 1: + IC(0.000 ns) + CELL(2.300 ns) = 2.300 ns; Loc. = PIN_40; Fanout = 34; CLK Node = 'CLK'" {  } { { "D:/RONTEC/POWER/PCI/Altera/db/testlatch_cmp.qrpt" "" { Report "D:/RONTEC/POWER/PCI/Altera/db/testlatch_cmp.qrpt" Compiler "testlatch" "UNKNOWN" "V1" "D:/RONTEC/POWER/PCI/Altera/db/testlatch.quartus_db" { Floorplan "D:/RONTEC/POWER/PCI/Altera/" "" "" { CLK } "NODE_NAME" } "" } } { "testlatch.bdf" "" { Schematic "D:/RONTEC/POWER/PCI/Altera/testlatch.bdf" { { 360 -616 -448 376 "CLK" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.300 ns) 3.600 ns JTAGcore:inst4\|direct 2 REG LC50 9 " "Info: 2: + IC(0.000 ns) + CELL(1.300 ns) = 3.600 ns; Loc. = LC50; Fanout = 9; REG Node = 'JTAGcore:inst4\|direct'" {  } { { "D:/RONTEC/POWER/PCI/Altera/db/testlatch_cmp.qrpt" "" { Report "D:/RONTEC/POWER/PCI/Altera/db/testlatch_cmp.qrpt" Compiler "testlatch" "UNKNOWN" "V1" "D:/RONTEC/POWER/PCI/Altera/db/testlatch.quartus_db" { Floorplan "D:/RONTEC/POWER/PCI/Altera/" "" "1.300 ns" { CLK JTAGcore:inst4|direct } "NODE_NAME" } "" } } { "JtagCore.V" "" { Text "D:/RONTEC/POWER/PCI/Altera/JtagCore.V" 102 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.600 ns 100.00 % " "Info: Total cell delay = 3.600 ns ( 100.00 % )" {  } {  } 0}  } { { "D:/RONTEC/POWER/PCI/Altera/db/testlatch_cmp.qrpt" "" { Report "D:/RONTEC/POWER/PCI/Altera/db/testlatch_cmp.qrpt" Compiler "testlatch" "UNKNOWN" "V1" "D:/RONTEC/POWER/PCI/Altera/db/testlatch.quartus_db" { Floorplan "D:/RONTEC/POWER/PCI/Altera/" "" "3.600 ns" { CLK JTAGcore:inst4|direct } "NODE_NAME" } "" } } { "e:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus42/bin/Technology_Viewer.qrui" "3.600 ns" { CLK CLK~out JTAGcore:inst4|direct } { 0.0ns 0.0ns 0.0ns } { 0.0ns 2.3ns 1.3ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK source 3.600 ns - Shortest register " "Info: - Shortest clock path from clock \"CLK\" to source register is 3.600 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.300 ns) 2.300 ns CLK 1 CLK PIN_40 34 " "Info: 1: + IC(0.000 ns) + CELL(2.300 ns) = 2.300 ns; Loc. = PIN_40; Fanout = 34; CLK Node = 'CLK'" {  } { { "D:/RONTEC/POWER/PCI/Altera/db/testlatch_cmp.qrpt" "" { Report "D:/RONTEC/POWER/PCI/Altera/db/testlatch_cmp.qrpt" Compiler "testlatch" "UNKNOWN" "V1" "D:/RONTEC/POWER/PCI/Altera/db/testlatch.quartus_db" { Floorplan "D:/RONTEC/POWER/PCI/Altera/" "" "" { CLK } "NODE_NAME" } "" } } { "testlatch.bdf" "" { Schematic "D:/RONTEC/POWER/PCI/Altera/testlatch.bdf" { { 360 -616 -448 376 "CLK" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.300 ns) 3.600 ns JTAGcore:inst4\|SM~126 2 REG LC23 50 " "Info: 2: + IC(0.000 ns) + CELL(1.300 ns) = 3.600 ns; Loc. = LC23; Fanout = 50; REG Node = 'JTAGcore:inst4\|SM~126'" {  } { { "D:/RONTEC/POWER/PCI/Altera/db/testlatch_cmp.qrpt" "" { Report "D:/RONTEC/POWER/PCI/Altera/db/testlatch_cmp.qrpt" Compiler "testlatch" "UNKNOWN" "V1" "D:/RONTEC/POWER/PCI/Altera/db/testlatch.quartus_db" { Floorplan "D:/RONTEC/POWER/PCI/Altera/" "" "1.300 ns" { CLK JTAGcore:inst4|SM~126 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.600 ns 100.00 % " "Info: Total cell delay = 3.600 ns ( 100.00 % )" {  } {  } 0}  } { { "D:/RONTEC/POWER/PCI/Altera/db/testlatch_cmp.qrpt" "" { Report "D:/RONTEC/POWER/PCI/Altera/db/testlatch_cmp.qrpt" Compiler "testlatch" "UNKNOWN" "V1" "D:/RONTEC/POWER/PCI/Altera/db/testlatch.quartus_db" { Floorplan "D:/RONTEC/POWER/PCI/Altera/" "" "3.600 ns" { CLK JTAGcore:inst4|SM~126 } "NODE_NAME" } "" } } { "e:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus42/bin/Technology_Viewer.qrui" "3.600 ns" { CLK CLK~out JTAGcore:inst4|SM~126 } { 0.0ns 0.0ns 0.0ns } { 0.0ns 2.3ns 1.3ns } } }  } 0}  } { { "D:/RONTEC/POWER/PCI/Altera/db/testlatch_cmp.qrpt" "" { Report "D:/RONTEC/POWER/PCI/Altera/db/testlatch_cmp.qrpt" Compiler "testlatch" "UNKNOWN" "V1" "D:/RONTEC/POWER/PCI/Altera/db/testlatch.quartus_db" { Floorplan "D:/RONTEC/POWER/PCI/Altera/" "" "3.600 ns" { CLK JTAGcore:inst4|direct } "NODE_NAME" } "" } } { "e:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus42/bin/Technology_Viewer.qrui" "3.600 ns" { CLK CLK~out JTAGcore:inst4|direct } { 0.0ns 0.0ns 0.0ns } { 0.0ns 2.3ns 1.3ns } } } { "D:/RONTEC/POWER/PCI/Altera/db/testlatch_cmp.qrpt" "" { Report "D:/RONTEC/POWER/PCI/Altera/db/testlatch_cmp.qrpt" Compiler "testlatch" "UNKNOWN" "V1" "D:/RONTEC/POWER/PCI/Altera/db/testlatch.quartus_db" { Floorplan "D:/RONTEC/POWER/PCI/Altera/" "" "3.600 ns" { CLK JTAGcore:inst4|SM~126 } "NODE_NAME" } "" } } { "e:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus42/bin/Technology_Viewer.qrui" "3.600 ns" { CLK CLK~out JTAGcore:inst4|SM~126 } { 0.0ns 0.0ns 0.0ns } { 0.0ns 2.3ns 1.3ns } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "1.600 ns - " "Info: - Micro clock to output delay of source is 1.600 ns" {  } {  } 0} { "Info" "ITDB_FULL_TH_DELAY" "1.300 ns + " "Info: + Micro hold delay of destination is 1.300 ns" {  } { { "JtagCore.V" "" { Text "D:/RONTEC/POWER/PCI/Altera/JtagCore.V" 102 -1 0 } }  } 0}  } { { "D:/RONTEC/POWER/PCI/Altera/db/testlatch_cmp.qrpt" "" { Report "D:/RONTEC/POWER/PCI/Altera/db/testlatch_cmp.qrpt" Compiler "testlatch" "UNKNOWN" "V1" "D:/RONTEC/POWER/PCI/Altera/db/testlatch.quartus_db" { Floorplan "D:/RONTEC/POWER/PCI/Altera/" "" "3.600 ns" { CLK JTAGcore:inst4|direct } "NODE_NAME" } "" } } { "e:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus42/bin/Technology_Viewer.qrui" "3.600 ns" { CLK CLK~out JTAGcore:inst4|direct } { 0.0ns 0.0ns 0.0ns } { 0.0ns 2.3ns 1.3ns } } } { "D:/RONTEC/POWER/PCI/Altera/db/testlatch_cmp.qrpt" "" { Report "D:/RONTEC/POWER/PCI/Altera/db/testlatch_cmp.qrpt" Compiler "testlatch" "UNKNOWN" "V1" "D:/RONTEC/POWER/PCI/Altera/db/testlatch.quartus_db" { Floorplan "D:/RONTEC/POWER/PCI/Altera/" "" "3.600 ns" { CLK JTAGcore:inst4|SM~126 } "NODE_NAME" } "" } } { "e:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus42/bin/Technology_Viewer.qrui" "3.600 ns" { CLK CLK~out JTAGcore:inst4|SM~126 } { 0.0ns 0.0ns 0.0ns } { 0.0ns 2.3ns 1.3ns } } }  } 0}  } { { "D:/RONTEC/POWER/PCI/Altera/db/testlatch_cmp.qrpt" "" { Report "D:/RONTEC/POWER/PCI/Altera/db/testlatch_cmp.qrpt" Compiler "testlatch" "UNKNOWN" "V1" "D:/RONTEC/POWER/PCI/Altera/db/testlatch.quartus_db" { Floorplan "D:/RONTEC/POWER/PCI/Altera/" "" "3.700 ns" { JTAGcore:inst4|SM~126 JTAGcore:inst4|direct } "NODE_NAME" } "" } } { "e:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus42/bin/Technology_Viewer.qrui" "3.700 ns" { JTAGcore:inst4|SM~126 JTAGcore:inst4|direct } { 0.0ns 2.5ns } { 0.0ns 1.2ns } } } { "D:/RONTEC/POWER/PCI/Altera/db/testlatch_cmp.qrpt" "" { Report "D:/RONTEC/POWER/PCI/Altera/db/testlatch_cmp.qrpt" Compiler "testlatch" "UNKNOWN" "V1" "D:/RONTEC/POWER/PCI/Altera/db/testlatch.quartus_db" { Floorplan "D:/RONTEC/POWER/PCI/Altera/" "" "3.600 ns" { CLK JTAGcore:inst4|direct } "NODE_NAME" } "" } } { "e:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus42/bin/Technology_Viewer.qrui" "3.600 ns" { CLK CLK~out JTAGcore:inst4|direct } { 0.0ns 0.0ns 0.0ns } { 0.0ns 2.3ns 1.3ns } } } { "D:/RONTEC/POWER/PCI/Altera/db/testlatch_cmp.qrpt" "" { Report "D:/RONTEC/POWER/PCI/Altera/db/testlatch_cmp.qrpt" Compiler "testlatch" "UNKNOWN" "V1" "D:/RONTEC/POWER/PCI/Altera/db/testlatch.quartus_db" { Floorplan "D:/RONTEC/POWER/PCI/Altera/" "" "3.600 ns" { CLK JTAGcore:inst4|SM~126 } "NODE_NAME" } "" } } { "e:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus42/bin/Technology_Viewer.qrui" "3.600 ns" { CLK CLK~out JTAGcore:inst4|SM~126 } { 0.0ns 0.0ns 0.0ns } { 0.0ns 2.3ns 1.3ns } } }  } 0}
{ "Info" "ITDB_TSU_RESULT" "JTAGcore:inst4\|SM~125 D\[5\] CLK 7.200 ns register " "Info: tsu for register \"JTAGcore:inst4\|SM~125\" (data pin = \"D\[5\]\", clock pin = \"CLK\") is 7.200 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "7.900 ns + Longest pin register " "Info: + Longest pin to register delay is 7.900 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns D\[5\] 1 PIN PIN_10 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PIN_10; Fanout = 1; PIN Node = 'D\[5\]'" {  } { { "D:/RONTEC/POWER/PCI/Altera/db/testlatch_cmp.qrpt" "" { Report "D:/RONTEC/POWER/PCI/Altera/db/testlatch_cmp.qrpt" Compiler "testlatch" "UNKNOWN" "V1" "D:/RONTEC/POWER/PCI/Altera/db/testlatch.quartus_db" { Floorplan "D:/RONTEC/POWER/PCI/Altera/" "" "" { D[5] } "NODE_NAME" } "" } } { "testlatch.bdf" "" { Schematic "D:/RONTEC/POWER/PCI/Altera/testlatch.bdf" { { 296 -272 -96 312 "D\[7..0\]" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.400 ns) 1.400 ns D~2 2 COMB IO25 9 " "Info: 2: + IC(0.000 ns) + CELL(1.400 ns) = 1.400 ns; Loc. = IO25; Fanout = 9; COMB Node = 'D~2'" {  } { { "D:/RONTEC/POWER/PCI/Altera/db/testlatch_cmp.qrpt" "" { Report "D:/RONTEC/POWER/PCI/Altera/db/testlatch_cmp.qrpt" Compiler "testlatch" "UNKNOWN" "V1" "D:/RONTEC/POWER/PCI/Altera/db/testlatch.quartus_db" { Floorplan "D:/RONTEC/POWER/PCI/Altera/" "" "1.400 ns" { D[5] D~2 } "NODE_NAME" } "" } } { "testlatch.bdf" "" { Schematic "D:/RONTEC/POWER/PCI/Altera/testlatch.bdf" { { 296 -272 -96 312 "D\[7..0\]" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.400 ns) + CELL(1.200 ns) 5.000 ns JTAGcore:inst4\|SM~985 3 COMB LC31 1 " "Info: 3: + IC(2.400 ns) + CELL(1.200 ns) = 5.000 ns; Loc. = LC31; Fanout = 1; COMB Node = 'JTAGcore:inst4\|SM~985'" {  } { { "D:/RONTEC/POWER/PCI/Altera/db/testlatch_cmp.qrpt" "" { Report "D:/RONTEC/POWER/PCI/Altera/db/testlatch_cmp.qrpt" Compiler "testlatch" "UNKNOWN" "V1" "D:/RONTEC/POWER/PCI/Altera/db/testlatch.quartus_db" { Floorplan "D:/RONTEC/POWER/PCI/Altera/" "" "3.600 ns" { D~2 JTAGcore:inst4|SM~985 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.900 ns) 7.900 ns JTAGcore:inst4\|SM~125 4 REG LC32 55 " "Info: 4: + IC(0.000 ns) + CELL(2.900 ns) = 7.900 ns; Loc. = LC32; Fanout = 55; REG Node = 'JTAGcore:inst4\|SM~125'" {  } { { "D:/RONTEC/POWER/PCI/Altera/db/testlatch_cmp.qrpt" "" { Report "D:/RONTEC/POWER/PCI/Altera/db/testlatch_cmp.qrpt" Compiler "testlatch" "UNKNOWN" "V1" "D:/RONTEC/POWER/PCI/Altera/db/testlatch.quartus_db" { Floorplan "D:/RONTEC/POWER/PCI/Altera/" "" "2.900 ns" { JTAGcore:inst4|SM~985 JTAGcore:inst4|SM~125 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "5.500 ns 69.62 % " "Info: Total cell delay = 5.500 ns ( 69.62 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.400 ns 30.38 % " "Info: Total interconnect delay = 2.400 ns ( 30.38 % )" {  } {  } 0}  } { { "D:/RONTEC/POWER/PCI/Altera/db/testlatch_cmp.qrpt" "" { Report "D:/RONTEC/POWER/PCI/Altera/db/testlatch_cmp.qrpt" Compiler "testlatch" "UNKNOWN" "V1" "D:/RONTEC/POWER/PCI/Altera/db/testlatch.quartus_db" { Floorplan "D:/RONTEC/POWER/PCI/Altera/" "" "7.900 ns" { D[5] D~2 JTAGcore:inst4|SM~985 JTAGcore:inst4|SM~125 } "NODE_NAME" } "" } } { "e:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus42/bin/Technology_Viewer.qrui" "7.900 ns" { D[5] D~2 JTAGcore:inst4|SM~985 JTAGcore:inst4|SM~125 } { 0.000ns 0.000ns 2.400ns 0.000ns } { 0.000ns 1.400ns 1.200ns 2.900ns } } }  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "2.900 ns + " "Info: + Micro setup delay of destination is 2.900 ns" {  } {  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK destination 3.600 ns - Shortest register " "Info: - Shortest clock path from clock \"CLK\" to destination register is 3.600 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.300 ns) 2.300 ns CLK 1 CLK PIN_40 34 " "Info: 1: + IC(0.000 ns) + CELL(2.300 ns) = 2.300 ns; Loc. = PIN_40; Fanout = 34; CLK Node = 'CLK'" {  } { { "D:/RONTEC/POWER/PCI/Altera/db/testlatch_cmp.qrpt" "" { Report "D:/RONTEC/POWER/PCI/Altera/db/testlatch_cmp.qrpt" Compiler "testlatch" "UNKNOWN" "V1" "D:/RONTEC/POWER/PCI/Altera/db/testlatch.quartus_db" { Floorplan "D:/RONTEC/POWER/PCI/Altera/" "" "" { CLK } "NODE_NAME" } "" } } { "testlatch.bdf" "" { Schematic "D:/RONTEC/POWER/PCI/Altera/testlatch.bdf" { { 360 -616 -448 376 "CLK" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.300 ns) 3.600 ns JTAGcore:inst4\|SM~125 2 REG LC32 55 " "Info: 2: + IC(0.000 ns) + CELL(1.300 ns) = 3.600 ns; Loc. = LC32; Fanout = 55; REG Node = 'JTAGcore:inst4\|SM~125'" {  } { { "D:/RONTEC/POWER/PCI/Altera/db/testlatch_cmp.qrpt" "" { Report "D:/RONTEC/POWER/PCI/Altera/db/testlatch_cmp.qrpt" Compiler "testlatch" "UNKNOWN" "V1" "D:/RONTEC/POWER/PCI/Altera/db/testlatch.quartus_db" { Floorplan "D:/RONTEC/POWER/PCI/Altera/" "" "1.300 ns" { CLK JTAGcore:inst4|SM~125 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.600 ns 100.00 % " "Info: Total cell delay = 3.600 ns ( 100.00 % )" {  } {  } 0}  } { { "D:/RONTEC/POWER/PCI/Altera/db/testlatch_cmp.qrpt" "" { Report "D:/RONTEC/POWER/PCI/Altera/db/testlatch_cmp.qrpt" Compiler "testlatch" "UNKNOWN" "V1" "D:/RONTEC/POWER/PCI/Altera/db/testlatch.quartus_db" { Floorplan "D:/RONTEC/POWER/PCI/Altera/" "" "3.600 ns" { CLK JTAGcore:inst4|SM~125 } "NODE_NAME" } "" } } { "e:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus42/bin/Technology_Viewer.qrui" "3.600 ns" { CLK CLK~out JTAGcore:inst4|SM~125 } { 0.000ns 0.000ns 0.000ns } { 0.000ns 2.300ns 1.300ns } } }  } 0}  } { { "D:/RONTEC/POWER/PCI/Altera/db/testlatch_cmp.qrpt" "" { Report "D:/RONTEC/POWER/PCI/Altera/db/testlatch_cmp.qrpt" Compiler "testlatch" "UNKNOWN" "V1" "D:/RONTEC/POWER/PCI/Altera/db/testlatch.quartus_db" { Floorplan "D:/RONTEC/POWER/PCI/Altera/" "" "7.900 ns" { D[5] D~2 JTAGcore:inst4|SM~985 JTAGcore:inst4|SM~125 } "NODE_NAME" } "" } } { "e:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus42/bin/Technology_Viewer.qrui" "7.900 ns" { D[5] D~2 JTAGcore:inst4|SM~985 JTAGcore:inst4|SM~125 } { 0.000ns 0.000ns 2.400ns 0.000ns } { 0.000ns 1.400ns 1.200ns 2.900ns } } } { "D:/RONTEC/POWER/PCI/Altera/db/testlatch_cmp.qrpt" "" { Report "D:/RONTEC/POWER/PCI/Altera/db/testlatch_cmp.qrpt" Compiler "testlatch" "UNKNOWN" "V1" "D:/RONTEC/POWER/PCI/Altera/db/testlatch.quartus_db" { Floorplan "D:/RONTEC/POWER/PCI/Altera/" "" "3.600 ns" { CLK JTAGcore:inst4|SM~125 } "NODE_NAME" } "" } } { "e:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus42/bin/Technology_Viewer.qrui" "3.600 ns" { CLK CLK~out JTAGcore:inst4|SM~125 } { 0.000ns 0.000ns 0.000ns } { 0.000ns 2.300ns 1.300ns } } }  } 0}
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