shift.tan.rpt

用verilog编写的USB下载线程序 实现USB协议和JTAG接口的数据转换实现状态机。

; N/A           ; None        ; -2.100 ns ; reset  ; shiftout:inst|shifter[0]  ; clk      ;
+---------------+-------------+-----------+--------+---------------------------+----------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Timing Analyzer
    Info: Version 4.2 Build 157 12/07/2004 SJ Full Version
    Info: Processing started: Tue Dec 27 17:38:10 2005
Info: Command: quartus_tan --import_settings_files=off --export_settings_files=off shift -c shift
Info: Started post-fitting delay annotation
Info: Delay annotation completed successfully
Info: Slack time is 29.9 ns for clock "clk" between source register "shiftout:inst|rdy" and destination register "shiftout:inst|T_CLK"
    Info: Fmax is 99.01 MHz (period= 10.1 ns)
    Info: + Largest register to register requirement is 35.500 ns
        Info: + Setup relationship between source and destination is 40.000 ns
            Info: + Latch edge is 40.000 ns
                Info: Clock period of Destination clock "clk" is 40.000 ns with  offset of 0.000 ns and duty cycle of 50
                Info: Multicycle Setup factor for Destination register is 1
            Info: - Launch edge is 0.000 ns
                Info: Clock period of Source clock "clk" is 40.000 ns with  offset of 0.000 ns and duty cycle of 50
                Info: Clock offset from Source is based on specified offset of 0.000 ns and phase shift of 0 degrees of the base clock
                Info: Multicycle Setup factor for Source register is 1
                Info: Clock offset from Destination is based on specified offset of 0.000 ns and phase shift of 0 degrees of the base clock
            Info: Clock setup uncertainty between source and destination is 0.000 ns
        Info: + Largest clock skew is 0.000 ns
            Info: + Shortest clock path from clock "clk" to destination register is 3.600 ns
                Info: 1: + IC(0.000 ns) + CELL(2.300 ns) = 2.300 ns; Loc. = PIN_37; Fanout = 14; CLK Node = 'clk'
                Info: 2: + IC(0.000 ns) + CELL(1.300 ns) = 3.600 ns; Loc. = LC3; Fanout = 33; REG Node = 'shiftout:inst|T_CLK'
                Info: Total cell delay = 3.600 ns ( 100.00 % )
            Info: - Longest clock path from clock "clk" to source register is 3.600 ns
                Info: 1: + IC(0.000 ns) + CELL(2.300 ns) = 2.300 ns; Loc. = PIN_37; Fanout = 14; CLK Node = 'clk'
                Info: 2: + IC(0.000 ns) + CELL(1.300 ns) = 3.600 ns; Loc. = LC4; Fanout = 55; REG Node = 'shiftout:inst|rdy'
                Info: Total cell delay = 3.600 ns ( 100.00 % )
        Info: - Micro clock to output delay of source is 1.600 ns
        Info: - Micro setup delay of destination is 2.900 ns
    Info: - Longest register to register delay is 5.600 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC4; Fanout = 55; REG Node = 'shiftout:inst|rdy'
        Info: 2: + IC(2.400 ns) + CELL(3.200 ns) = 5.600 ns; Loc. = LC3; Fanout = 33; REG Node = 'shiftout:inst|T_CLK'
        Info: Total cell delay = 3.200 ns ( 57.14 % )
        Info: Total interconnect delay = 2.400 ns ( 42.86 % )
Info: Minimum slack time is 5.8 ns for clock "clk" between source register "shiftout:inst|bitcount[1]" and destination register "shiftout:inst|T_CLK"
    Info: + Shortest register to register delay is 5.500 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC8; Fanout = 11; REG Node = 'shiftout:inst|bitcount[1]'
        Info: 2: + IC(2.300 ns) + CELL(3.200 ns) = 5.500 ns; Loc. = LC3; Fanout = 33; REG Node = 'shiftout:inst|T_CLK'
        Info: Total cell delay = 3.200 ns ( 58.18 % )
        Info: Total interconnect delay = 2.300 ns ( 41.82 % )
    Info: - Smallest register to register requirement is -0.300 ns
        Info: + Hold relationship between source and destination is 0.000 ns
            Info: + Latch edge is 0.000 ns
                Info: Clock period of Destination clock "clk" is 40.000 ns with  offset of 0.000 ns and duty cycle of 50
                Info: Multicycle Setup factor for Destination register is 1
                Info: Multicycle Hold factor for Destination register is 1
            Info: - Launch edge is 0.000 ns
                Info: Clock period of Source clock "clk" is 40.000 ns with  offset of 0.000 ns and duty cycle of 50
                Info: Clock offset from Source is based on specified offset of 0.000 ns and phase shift of 0 degrees of the base clock
                Info: Multicycle Setup factor for Source register is 1
                Info: Multicycle Hold factor for Source register is 1
                Info: Clock offset from Destination is based on specified offset of 0.000 ns and phase shift of 0 degrees of the base clock
            Info: Clock hold uncertainty between source and destination is 0.000 ns
        Info: + Smallest clock skew is 0.000 ns
            Info: + Longest clock path from clock "clk" to destination register is 3.600 ns
                Info: 1: + IC(0.000 ns) + CELL(2.300 ns) = 2.300 ns; Loc. = PIN_37; Fanout = 14; CLK Node = 'clk'
                Info: 2: + IC(0.000 ns) + CELL(1.300 ns) = 3.600 ns; Loc. = LC3; Fanout = 33; REG Node = 'shiftout:inst|T_CLK'
                Info: Total cell delay = 3.600 ns ( 100.00 % )
            Info: - Shortest clock path from clock "clk" to source register is 3.600 ns
                Info: 1: + IC(0.000 ns) + CELL(2.300 ns) = 2.300 ns; Loc. = PIN_37; Fanout = 14; CLK Node = 'clk'
                Info: 2: + IC(0.000 ns) + CELL(1.300 ns) = 3.600 ns; Loc. = LC8; Fanout = 11; REG Node = 'shiftout:inst|bitcount[1]'
                Info: Total cell delay = 3.600 ns ( 100.00 % )
        Info: - Micro clock to output delay of source is 1.600 ns
        Info: + Micro hold delay of destination is 1.300 ns
Info: tsu for register "shiftout:inst|rdy" (data pin = "load", clock pin = "clk") is 6.300 ns
    Info: + Longest pin to register delay is 7.000 ns
        Info: 1: + IC(0.000 ns) + CELL(1.400 ns) = 1.400 ns; Loc. = PIN_34; Fanout = 21; PIN Node = 'load'
        Info: 2: + IC(2.400 ns) + CELL(3.200 ns) = 7.000 ns; Loc. = LC4; Fanout = 55; REG Node = 'shiftout:inst|rdy'
        Info: Total cell delay = 4.600 ns ( 65.71 % )
        Info: Total interconnect delay = 2.400 ns ( 34.29 % )
    Info: + Micro setup delay of destination is 2.900 ns
    Info: - Shortest clock path from clock "clk" to destination register is 3.600 ns
        Info: 1: + IC(0.000 ns) + CELL(2.300 ns) = 2.300 ns; Loc. = PIN_37; Fanout = 14; CLK Node = 'clk'
        Info: 2: + IC(0.000 ns) + CELL(1.300 ns) = 3.600 ns; Loc. = LC4; Fanout = 55; REG Node = 'shiftout:inst|rdy'
        Info: Total cell delay = 3.600 ns ( 100.00 % )
Info: tco from clock "clk" to destination pin "so" through register "shiftout:inst|shifter[0]" is 13.800 ns
    Info: + Longest clock path from clock "clk" to source register is 3.600 ns
        Info: 1: + IC(0.000 ns) + CELL(2.300 ns) = 2.300 ns; Loc. = PIN_37; Fanout = 14; CLK Node = 'clk'
        Info: 2: + IC(0.000 ns) + CELL(1.300 ns) = 3.600 ns; Loc. = LC19; Fanout = 7; REG Node = 'shiftout:inst|shifter[0]'
        Info: Total cell delay = 3.600 ns ( 100.00 % )
    Info: + Micro clock to output delay of source is 1.600 ns
    Info: + Longest register to pin delay is 8.600 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC19; Fanout = 7; REG Node = 'shiftout:inst|shifter[0]'
        Info: 2: + IC(2.300 ns) + CELL(4.500 ns) = 6.800 ns; Loc. = LC17; Fanout = 1; COMB Node = 'shiftout:inst|shifter[0]~292'
        Info: 3: + IC(0.000 ns) + CELL(1.800 ns) = 8.600 ns; Loc. = PIN_15; Fanout = 0; PIN Node = 'so'
        Info: Total cell delay = 6.300 ns ( 73.26 % )
        Info: Total interconnect delay = 2.300 ns ( 26.74 % )
Info: th for register "shiftout:inst|shifter[0]" (data pin = "din[0]", clock pin = "clk") is -2.000 ns
    Info: + Longest clock path from clock "clk" to destination register is 3.600 ns
        Info: 1: + IC(0.000 ns) + CELL(2.300 ns) = 2.300 ns; Loc. = PIN_37; Fanout = 14; CLK Node = 'clk'
        Info: 2: + IC(0.000 ns) + CELL(1.300 ns) = 3.600 ns; Loc. = LC19; Fanout = 7; REG Node = 'shiftout:inst|shifter[0]'
        Info: Total cell delay = 3.600 ns ( 100.00 % )
    Info: + Micro hold delay of destination is 1.300 ns
    Info: - Shortest pin to register delay is 6.900 ns
        Info: 1: + IC(0.000 ns) + CELL(1.400 ns) = 1.400 ns; Loc. = PIN_22; Fanout = 2; PIN Node = 'din[0]'
        Info: 2: + IC(2.300 ns) + CELL(3.200 ns) = 6.900 ns; Loc. = LC19; Fanout = 7; REG Node = 'shiftout:inst|shifter[0]'
        Info: Total cell delay = 4.600 ns ( 66.67 % )
        Info: Total interconnect delay = 2.300 ns ( 33.33 % )
Info: All timing requirements were met. See Report window for more details.
Info: Quartus II Timing Analyzer was successful. 0 errors, 0 warnings
    Info: Processing ended: Tue Dec 27 17:38:10 2005
    Info: Elapsed time: 00:00:01