shift.tan.summary

用verilog编写的USB下载线程序 实现USB协议和JTAG接口的数据转换实现状态机。

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Timing Analyzer Summary
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Type           : Worst-case tsu
Slack          : N/A
Required Time  : None
Actual Time    : 6.300 ns
From           : reset
To             : shiftout:inst|shifter[0]
From Clock     : 
To Clock       : clk
Failed Paths   : 0

Type           : Worst-case tco
Slack          : N/A
Required Time  : None
Actual Time    : 13.800 ns
From           : shiftout:inst|shifter[0]
To             : so
From Clock     : clk
To Clock       : 
Failed Paths   : 0

Type           : Worst-case th
Slack          : N/A
Required Time  : None
Actual Time    : -2.000 ns
From           : si
To             : shiftout:inst|shifter[7]
From Clock     : 
To Clock       : clk
Failed Paths   : 0

Type           : Clock Setup: 'clk'
Slack          : 29.900 ns
Required Time  : 25.00 MHz ( period = 40.000 ns )
Actual Time    : 99.01 MHz ( period = 10.100 ns )
From           : shiftout:inst|rdy
To             : shiftout:inst|T_CLK
From Clock     : clk
To Clock       : clk
Failed Paths   : 0

Type           : Clock Hold: 'clk'
Slack          : 5.800 ns
Required Time  : 25.00 MHz ( period = 40.000 ns )
Actual Time    : N/A
From           : shiftout:inst|bitcount[1]
To             : shiftout:inst|T_CLK
From Clock     : clk
To Clock       : clk
Failed Paths   : 0

Type           : Total number of failed paths
Slack          : 
Required Time  : 
Actual Time    : 
From           : 
To             : 
From Clock     : 
To Clock       : 
Failed Paths   : 0

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