📄 shift.tan.qmsg
字号:
{ "Info" "ITDB_FULL_SLACK_RESULT" "clk register shiftout:inst\|rdy register shiftout:inst\|T_CLK 29.9 ns " "Info: Slack time is 29.9 ns for clock \"clk\" between source register \"shiftout:inst\|rdy\" and destination register \"shiftout:inst\|T_CLK\"" { { "Info" "ITDB_SIMPLE_FMAX_RESULT" "99.01 MHz 10.1 ns " "Info: Fmax is 99.01 MHz (period= 10.1 ns)" { } { } 0} { "Info" "ITDB_FULL_P2P_REQUIREMENT_RESULT" "35.500 ns + Largest register register " "Info: + Largest register to register requirement is 35.500 ns" { { "Info" "ITDB_FULL_SETUP_REQUIREMENT" "40.000 ns + " "Info: + Setup relationship between source and destination is 40.000 ns" { { "Info" "ITDB_EDGE_RESULT" "+ Latch 40.000 ns " "Info: + Latch edge is 40.000 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Destination clk 40.000 ns 0.000 ns 50 " "Info: Clock period of Destination clock \"clk\" is 40.000 ns with offset of 0.000 ns and duty cycle of 50" { } { } 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Destination Setup 1 " "Info: Multicycle Setup factor for Destination register is 1" { } { } 0} } { } 0} { "Info" "ITDB_EDGE_RESULT" "- Launch 0.000 ns " "Info: - Launch edge is 0.000 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Source clk 40.000 ns 0.000 ns 50 " "Info: Clock period of Source clock \"clk\" is 40.000 ns with offset of 0.000 ns and duty cycle of 50" { } { } 0} { "Info" "ITDB_CLOCK_OFFSET_COMPONENTS" "Source 0.000 ns 0 degrees " "Info: Clock offset from Source is based on specified offset of 0.000 ns and phase shift of 0 degrees of the base clock" { } { } 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Source Setup 1 " "Info: Multicycle Setup factor for Source register is 1" { } { } 0} { "Info" "ITDB_CLOCK_OFFSET_COMPONENTS" "Destination 0.000 ns 0 degrees " "Info: Clock offset from Destination is based on specified offset of 0.000 ns and phase shift of 0 degrees of the base clock" { } { } 0} } { } 0} { "Info" "ITDB_SETUP_UNCERTAINTY" "0.000 ns " "Info: Clock setup uncertainty between source and destination is 0.000 ns" { } { } 0} } { } 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns + Largest " "Info: + Largest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 3.600 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 3.600 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.300 ns) 2.300 ns clk 1 CLK PIN_37 14 " "Info: 1: + IC(0.000 ns) + CELL(2.300 ns) = 2.300 ns; Loc. = PIN_37; Fanout = 14; CLK Node = 'clk'" { } { { "D:/RONTEC/POWER/PCI/Altera/shift/db/shift_cmp.qrpt" "" { Report "D:/RONTEC/POWER/PCI/Altera/shift/db/shift_cmp.qrpt" Compiler "shift" "UNKNOWN" "V1" "D:/RONTEC/POWER/PCI/Altera/shift/db/shift.quartus_db" { Floorplan "D:/RONTEC/POWER/PCI/Altera/shift/" "" "" { clk } "NODE_NAME" } "" } } { "shift.bdf" "" { Schematic "D:/RONTEC/POWER/PCI/Altera/shift/shift.bdf" { { 248 368 536 264 "clk" "" } } } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.300 ns) 3.600 ns shiftout:inst\|T_CLK 2 REG LC3 33 " "Info: 2: + IC(0.000 ns) + CELL(1.300 ns) = 3.600 ns; Loc. = LC3; Fanout = 33; REG Node = 'shiftout:inst\|T_CLK'" { } { { "D:/RONTEC/POWER/PCI/Altera/shift/db/shift_cmp.qrpt" "" { Report "D:/RONTEC/POWER/PCI/Altera/shift/db/shift_cmp.qrpt" Compiler "shift" "UNKNOWN" "V1" "D:/RONTEC/POWER/PCI/Altera/shift/db/shift.quartus_db" { Floorplan "D:/RONTEC/POWER/PCI/Altera/shift/" "" "1.300 ns" { clk shiftout:inst|T_CLK } "NODE_NAME" } "" } } { "shiftout.v" "" { Text "D:/RONTEC/POWER/PCI/Altera/shift/shiftout.v" 11 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.600 ns 100.00 % " "Info: Total cell delay = 3.600 ns ( 100.00 % )" { } { } 0} } { { "D:/RONTEC/POWER/PCI/Altera/shift/db/shift_cmp.qrpt" "" { Report "D:/RONTEC/POWER/PCI/Altera/shift/db/shift_cmp.qrpt" Compiler "shift" "UNKNOWN" "V1" "D:/RONTEC/POWER/PCI/Altera/shift/db/shift.quartus_db" { Floorplan "D:/RONTEC/POWER/PCI/Altera/shift/" "" "3.600 ns" { clk shiftout:inst|T_CLK } "NODE_NAME" } "" } } { "e:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus42/bin/Technology_Viewer.qrui" "3.600 ns" { clk clk~out shiftout:inst|T_CLK } { 0.000ns 0.000ns 0.000ns } { 0.000ns 2.300ns 1.300ns } } } } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 3.600 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 3.600 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.300 ns) 2.300 ns clk 1 CLK PIN_37 14 " "Info: 1: + IC(0.000 ns) + CELL(2.300 ns) = 2.300 ns; Loc. = PIN_37; Fanout = 14; CLK Node = 'clk'" { } { { "D:/RONTEC/POWER/PCI/Altera/shift/db/shift_cmp.qrpt" "" { Report "D:/RONTEC/POWER/PCI/Altera/shift/db/shift_cmp.qrpt" Compiler "shift" "UNKNOWN" "V1" "D:/RONTEC/POWER/PCI/Altera/shift/db/shift.quartus_db" { Floorplan "D:/RONTEC/POWER/PCI/Altera/shift/" "" "" { clk } "NODE_NAME" } "" } } { "shift.bdf" "" { Schematic "D:/RONTEC/POWER/PCI/Altera/shift/shift.bdf" { { 248 368 536 264 "clk" "" } } } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.300 ns) 3.600 ns shiftout:inst\|rdy 2 REG LC4 55 " "Info: 2: + IC(0.000 ns) + CELL(1.300 ns) = 3.600 ns; Loc. = LC4; Fanout = 55; REG Node = 'shiftout:inst\|rdy'" { } { { "D:/RONTEC/POWER/PCI/Altera/shift/db/shift_cmp.qrpt" "" { Report "D:/RONTEC/POWER/PCI/Altera/shift/db/shift_cmp.qrpt" Compiler "shift" "UNKNOWN" "V1" "D:/RONTEC/POWER/PCI/Altera/shift/db/shift.quartus_db" { Floorplan "D:/RONTEC/POWER/PCI/Altera/shift/" "" "1.300 ns" { clk shiftout:inst|rdy } "NODE_NAME" } "" } } { "shiftout.v" "" { Text "D:/RONTEC/POWER/PCI/Altera/shift/shiftout.v" 10 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.600 ns 100.00 % " "Info: Total cell delay = 3.600 ns ( 100.00 % )" { } { } 0} } { { "D:/RONTEC/POWER/PCI/Altera/shift/db/shift_cmp.qrpt" "" { Report "D:/RONTEC/POWER/PCI/Altera/shift/db/shift_cmp.qrpt" Compiler "shift" "UNKNOWN" "V1" "D:/RONTEC/POWER/PCI/Altera/shift/db/shift.quartus_db" { Floorplan "D:/RONTEC/POWER/PCI/Altera/shift/" "" "3.600 ns" { clk shiftout:inst|rdy } "NODE_NAME" } "" } } { "e:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus42/bin/Technology_Viewer.qrui" "3.600 ns" { clk clk~out shiftout:inst|rdy } { 0.000ns 0.000ns 0.000ns } { 0.000ns 2.300ns 1.300ns } } } } 0} } { { "D:/RONTEC/POWER/PCI/Altera/shift/db/shift_cmp.qrpt" "" { Report "D:/RONTEC/POWER/PCI/Altera/shift/db/shift_cmp.qrpt" Compiler "shift" "UNKNOWN" "V1" "D:/RONTEC/POWER/PCI/Altera/shift/db/shift.quartus_db" { Floorplan "D:/RONTEC/POWER/PCI/Altera/shift/" "" "3.600 ns" { clk shiftout:inst|T_CLK } "NODE_NAME" } "" } } { "e:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus42/bin/Technology_Viewer.qrui" "3.600 ns" { clk clk~out shiftout:inst|T_CLK } { 0.000ns 0.000ns 0.000ns } { 0.000ns 2.300ns 1.300ns } } } { "D:/RONTEC/POWER/PCI/Altera/shift/db/shift_cmp.qrpt" "" { Report "D:/RONTEC/POWER/PCI/Altera/shift/db/shift_cmp.qrpt" Compiler "shift" "UNKNOWN" "V1" "D:/RONTEC/POWER/PCI/Altera/shift/db/shift.quartus_db" { Floorplan "D:/RONTEC/POWER/PCI/Altera/shift/" "" "3.600 ns" { clk shiftout:inst|rdy } "NODE_NAME" } "" } } { "e:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus42/bin/Technology_Viewer.qrui" "3.600 ns" { clk clk~out shiftout:inst|rdy } { 0.000ns 0.000ns 0.000ns } { 0.000ns 2.300ns 1.300ns } } } } 0} { "Info" "ITDB_FULL_TCO_DELAY" "1.600 ns - " "Info: - Micro clock to output delay of source is 1.600 ns" { } { { "shiftout.v" "" { Text "D:/RONTEC/POWER/PCI/Altera/shift/shiftout.v" 10 -1 0 } } } 0} { "Info" "ITDB_FULL_TSU_DELAY" "2.900 ns - " "Info: - Micro setup delay of destination is 2.900 ns" { } { { "shiftout.v" "" { Text "D:/RONTEC/POWER/PCI/Altera/shift/shiftout.v" 11 -1 0 } } } 0} } { { "D:/RONTEC/POWER/PCI/Altera/shift/db/shift_cmp.qrpt" "" { Report "D:/RONTEC/POWER/PCI/Altera/shift/db/shift_cmp.qrpt" Compiler "shift" "UNKNOWN" "V1" "D:/RONTEC/POWER/PCI/Altera/shift/db/shift.quartus_db" { Floorplan "D:/RONTEC/POWER/PCI/Altera/shift/" "" "3.600 ns" { clk shiftout:inst|T_CLK } "NODE_NAME" } "" } } { "e:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus42/bin/Technology_Viewer.qrui" "3.600 ns" { clk clk~out shiftout:inst|T_CLK } { 0.000ns 0.000ns 0.000ns } { 0.000ns 2.300ns 1.300ns } } } { "D:/RONTEC/POWER/PCI/Altera/shift/db/shift_cmp.qrpt" "" { Report "D:/RONTEC/POWER/PCI/Altera/shift/db/shift_cmp.qrpt" Compiler "shift" "UNKNOWN" "V1" "D:/RONTEC/POWER/PCI/Altera/shift/db/shift.quartus_db" { Floorplan "D:/RONTEC/POWER/PCI/Altera/shift/" "" "3.600 ns" { clk shiftout:inst|rdy } "NODE_NAME" } "" } } { "e:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus42/bin/Technology_Viewer.qrui" "3.600 ns" { clk clk~out shiftout:inst|rdy } { 0.000ns 0.000ns 0.000ns } { 0.000ns 2.300ns 1.300ns } } } } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.600 ns - Longest register register " "Info: - Longest register to register delay is 5.600 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns shiftout:inst\|rdy 1 REG LC4 55 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC4; Fanout = 55; REG Node = 'shiftout:inst\|rdy'" { } { { "D:/RONTEC/POWER/PCI/Altera/shift/db/shift_cmp.qrpt" "" { Report "D:/RONTEC/POWER/PCI/Altera/shift/db/shift_cmp.qrpt" Compiler "shift" "UNKNOWN" "V1" "D:/RONTEC/POWER/PCI/Altera/shift/db/shift.quartus_db" { Floorplan "D:/RONTEC/POWER/PCI/Altera/shift/" "" "" { shiftout:inst|rdy } "NODE_NAME" } "" } } { "shiftout.v" "" { Text "D:/RONTEC/POWER/PCI/Altera/shift/shiftout.v" 10 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.400 ns) + CELL(3.200 ns) 5.600 ns shiftout:inst\|T_CLK 2 REG LC3 33 " "Info: 2: + IC(2.400 ns) + CELL(3.200 ns) = 5.600 ns; Loc. = LC3; Fanout = 33; REG Node = 'shiftout:inst\|T_CLK'" { } { { "D:/RONTEC/POWER/PCI/Altera/shift/db/shift_cmp.qrpt" "" { Report "D:/RONTEC/POWER/PCI/Altera/shift/db/shift_cmp.qrpt" Compiler "shift" "UNKNOWN" "V1" "D:/RONTEC/POWER/PCI/Altera/shift/db/shift.quartus_db" { Floorplan "D:/RONTEC/POWER/PCI/Altera/shift/" "" "5.600 ns" { shiftout:inst|rdy shiftout:inst|T_CLK } "NODE_NAME" } "" } } { "shiftout.v" "" { Text "D:/RONTEC/POWER/PCI/Altera/shift/shiftout.v" 11 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.200 ns 57.14 % " "Info: Total cell delay = 3.200 ns ( 57.14 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.400 ns 42.86 % " "Info: Total interconnect delay = 2.400 ns ( 42.86 % )" { } { } 0} } { { "D:/RONTEC/POWER/PCI/Altera/shift/db/shift_cmp.qrpt" "" { Report "D:/RONTEC/POWER/PCI/Altera/shift/db/shift_cmp.qrpt" Compiler "shift" "UNKNOWN" "V1" "D:/RONTEC/POWER/PCI/Altera/shift/db/shift.quartus_db" { Floorplan "D:/RONTEC/POWER/PCI/Altera/shift/" "" "5.600 ns" { shiftout:inst|rdy shiftout:inst|T_CLK } "NODE_NAME" } "" } } { "e:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus42/bin/Technology_Viewer.qrui" "5.600 ns" { shiftout:inst|rdy shiftout:inst|T_CLK } { 0.000ns 2.400ns } { 0.000ns 3.200ns } } } } 0} } { { "D:/RONTEC/POWER/PCI/Altera/shift/db/shift_cmp.qrpt" "" { Report "D:/RONTEC/POWER/PCI/Altera/shift/db/shift_cmp.qrpt" Compiler "shift" "UNKNOWN" "V1" "D:/RONTEC/POWER/PCI/Altera/shift/db/shift.quartus_db" { Floorplan "D:/RONTEC/POWER/PCI/Altera/shift/" "" "3.600 ns" { clk shiftout:inst|T_CLK } "NODE_NAME" } "" } } { "e:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus42/bin/Technology_Viewer.qrui" "3.600 ns" { clk clk~out shiftout:inst|T_CLK } { 0.000ns 0.000ns 0.000ns } { 0.000ns 2.300ns 1.300ns } } } { "D:/RONTEC/POWER/PCI/Altera/shift/db/shift_cmp.qrpt" "" { Report "D:/RONTEC/POWER/PCI/Altera/shift/db/shift_cmp.qrpt" Compiler "shift" "UNKNOWN" "V1" "D:/RONTEC/POWER/PCI/Altera/shift/db/shift.quartus_db" { Floorplan "D:/RONTEC/POWER/PCI/Altera/shift/" "" "3.600 ns" { clk shiftout:inst|rdy } "NODE_NAME" } "" } } { "e:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus42/bin/Technology_Viewer.qrui" "3.600 ns" { clk clk~out shiftout:inst|rdy } { 0.000ns 0.000ns 0.000ns } { 0.000ns 2.300ns 1.300ns } } } { "D:/RONTEC/POWER/PCI/Altera/shift/db/shift_cmp.qrpt" "" { Report "D:/RONTEC/POWER/PCI/Altera/shift/db/shift_cmp.qrpt" Compiler "shift" "UNKNOWN" "V1" "D:/RONTEC/POWER/PCI/Altera/shift/db/shift.quartus_db" { Floorplan "D:/RONTEC/POWER/PCI/Altera/shift/" "" "5.600 ns" { shiftout:inst|rdy shiftout:inst|T_CLK } "NODE_NAME" } "" } } { "e:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus42/bin/Technology_Viewer.qrui" "5.600 ns" { shiftout:inst|rdy shiftout:inst|T_CLK } { 0.000ns 2.400ns } { 0.000ns 3.200ns } } } } 0}
{ "Info" "ITDB_FULL_MIN_SLACK_RESULT" "clk register shiftout:inst\|bitcount\[1\] register shiftout:inst\|T_CLK 5.8 ns " "Info: Minimum slack time is 5.8 ns for clock \"clk\" between source register \"shiftout:inst\|bitcount\[1\]\" and destination register \"shiftout:inst\|T_CLK\"" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.500 ns + Shortest register register " "Info: + Shortest register to register delay is 5.500 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns shiftout:inst\|bitcount\[1\] 1 REG LC8 11 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC8; Fanout = 11; REG Node = 'shiftout:inst\|bitcount\[1\]'" { } { { "D:/RONTEC/POWER/PCI/Altera/shift/db/shift_cmp.qrpt" "" { Report "D:/RONTEC/POWER/PCI/Altera/shift/db/shift_cmp.qrpt" Compiler "shift" "UNKNOWN" "V1" "D:/RONTEC/POWER/PCI/Altera/shift/db/shift.quartus_db" { Floorplan "D:/RONTEC/POWER/PCI/Altera/shift/" "" "" { shiftout:inst|bitcount[1] } "NODE_NAME" } "" } } { "shiftout.v" "" { Text "D:/RONTEC/POWER/PCI/Altera/shift/shiftout.v" 61 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.300 ns) + CELL(3.200 ns) 5.500 ns shiftout:inst\|T_CLK 2 REG LC3 33 " "Info: 2: + IC(2.300 ns) + CELL(3.200 ns) = 5.500 ns; Loc. = LC3; Fanout = 33; REG Node = 'shiftout:inst\|T_CLK'" { } { { "D:/RONTEC/POWER/PCI/Altera/shift/db/shift_cmp.qrpt" "" { Report "D:/RONTEC/POWER/PCI/Altera/shift/db/shift_cmp.qrpt" Compiler "shift" "UNKNOWN" "V1" "D:/RONTEC/POWER/PCI/Altera/shift/db/shift.quartus_db" { Floorplan "D:/RONTEC/POWER/PCI/Altera/shift/" "" "5.500 ns" { shiftout:inst|bitcount[1] shiftout:inst|T_CLK } "NODE_NAME" } "" } } { "shiftout.v" "" { Text "D:/RONTEC/POWER/PCI/Altera/shift/shiftout.v" 11 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.200 ns 58.18 % " "Info: Total cell delay = 3.200 ns ( 58.18 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.300 ns 41.82 % " "Info: Total interconnect delay = 2.300 ns ( 41.82 % )" { } { } 0} } { { "D:/RONTEC/POWER/PCI/Altera/shift/db/shift_cmp.qrpt" "" { Report "D:/RONTEC/POWER/PCI/Altera/shift/db/shift_cmp.qrpt" Compiler "shift" "UNKNOWN" "V1" "D:/RONTEC/POWER/PCI/Altera/shift/db/shift.quartus_db" { Floorplan "D:/RONTEC/POWER/PCI/Altera/shift/" "" "5.500 ns" { shiftout:inst|bitcount[1] shiftout:inst|T_CLK } "NODE_NAME" } "" } } { "e:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus42/bin/Technology_Viewer.qrui" "5.500 ns" { shiftout:inst|bitcount[1] shiftout:inst|T_CLK } { 0.0ns 2.3ns } { 0.0ns 3.2ns } } } } 0} { "Info" "ITDB_FULL_P2P_REQUIREMENT_RESULT" "-0.300 ns - Smallest register register " "Info: - Smallest register to register requirement is -0.300 ns" { { "Info" "ITDB_FULL_HOLD_REQUIREMENT" "0.000 ns + " "Info: + Hold relationship between source and destination is 0.000 ns" { { "Info" "ITDB_EDGE_RESULT" "+ Latch 0.000 ns " "Info: + Latch edge is 0.000 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Destination clk 40.000 ns 0.000 ns 50 " "Info: Clock period of Destination clock \"clk\" is 40.000 ns with offset of 0.000 ns and duty cycle of 50" { } { } 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Destination Setup 1 " "Info: Multicycle Setup factor for Destination register is 1" { } { } 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Destination Hold 1 " "Info: Multicycle Hold factor for Destination register is 1" { } { } 0} } { } 0} { "Info" "ITDB_EDGE_RESULT" "- Launch 0.000 ns " "Info: - Launch edge is 0.000 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Source clk 40.000 ns 0.000 ns 50 " "Info: Clock period of Source clock \"clk\" is 40.000 ns with offset of 0.000 ns and duty cycle of 50" { } { } 0} { "Info" "ITDB_CLOCK_OFFSET_COMPONENTS" "Source 0.000 ns 0 degrees " "Info: Clock offset from Source is based on specified offset of 0.000 ns and phase shift of 0 degrees of the base clock" { } { } 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Source Setup 1 " "Info: Multicycle Setup factor for Source register is 1" { } { } 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Source Hold 1 " "Info: Multicycle Hold factor for Source register is 1" { } { } 0} { "Info" "ITDB_CLOCK_OFFSET_COMPONENTS" "Destination 0.000 ns 0 degrees " "Info: Clock offset from Destination is based on specified offset of 0.000 ns and phase shift of 0 degrees of the base clock" { } { } 0} } { } 0} { "Info" "ITDB_HOLD_UNCERTAINTY" "0.000 ns " "Info: Clock hold uncertainty between source and destination is 0.000 ns" { } { } 0} } { } 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns + Smallest " "Info: + Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 3.600 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to destination register is 3.600 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.300 ns) 2.300 ns clk 1 CLK PIN_37 14 " "Info: 1: + IC(0.000 ns) + CELL(2.300 ns) = 2.300 ns; Loc. = PIN_37; Fanout = 14; CLK Node = 'clk'" { } { { "D:/RONTEC/POWER/PCI/Altera/shift/db/shift_cmp.qrpt" "" { Report "D:/RONTEC/POWER/PCI/Altera/shift/db/shift_cmp.qrpt" Compiler "shift" "UNKNOWN" "V1" "D:/RONTEC/POWER/PCI/Altera/shift/db/shift.quartus_db" { Floorplan "D:/RONTEC/POWER/PCI/Altera/shift/" "" "" { clk } "NODE_NAME" } "" } } { "shift.bdf" "" { Schematic "D:/RONTEC/POWER/PCI/Altera/shift/shift.bdf" { { 248 368 536 264 "clk" "" } } } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.300 ns) 3.600 ns shiftout:inst\|T_CLK 2 REG LC3 33 " "Info: 2: + IC(0.000 ns) + CELL(1.300 ns) = 3.600 ns; Loc. = LC3; Fanout = 33; REG Node = 'shiftout:inst\|T_CLK'" { } { { "D:/RONTEC/POWER/PCI/Altera/shift/db/shift_cmp.qrpt" "" { Report "D:/RONTEC/POWER/PCI/Altera/shift/db/shift_cmp.qrpt" Compiler "shift" "UNKNOWN" "V1" "D:/RONTEC/POWER/PCI/Altera/shift/db/shift.quartus_db" { Floorplan "D:/RONTEC/POWER/PCI/Altera/shift/" "" "1.300 ns" { clk shiftout:inst|T_CLK } "NODE_NAME" } "" } } { "shiftout.v" "" { Text "D:/RONTEC/POWER/PCI/Altera/shift/shiftout.v" 11 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.600 ns 100.00 % " "Info: Total cell delay = 3.600 ns ( 100.00 % )" { } { } 0} } { { "D:/RONTEC/POWER/PCI/Altera/shift/db/shift_cmp.qrpt" "" { Report "D:/RONTEC/POWER/PCI/Altera/shift/db/shift_cmp.qrpt" Compiler "shift" "UNKNOWN" "V1" "D:/RONTEC/POWER/PCI/Altera/shift/db/shift.quartus_db" { Floorplan "D:/RONTEC/POWER/PCI/Altera/shift/" "" "3.600 ns" { clk shiftout:inst|T_CLK } "NODE_NAME" } "" } } { "e:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus42/bin/Technology_Viewer.qrui" "3.600 ns" { clk clk~out shiftout:inst|T_CLK } { 0.0ns 0.0ns 0.0ns } { 0.0ns 2.3ns 1.3ns } } } } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 3.600 ns - Shortest register " "Info: - Shortest clock path from clock \"clk\" to source register is 3.600 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.300 ns) 2.300 ns clk 1 CLK PIN_37 14 " "Info: 1: + IC(0.000 ns) + CELL(2.300 ns) = 2.300 ns; Loc. = PIN_37; Fanout = 14; CLK Node = 'clk'" { } { { "D:/RONTEC/POWER/PCI/Altera/shift/db/shift_cmp.qrpt" "" { Report "D:/RONTEC/POWER/PCI/Altera/shift/db/shift_cmp.qrpt" Compiler "shift" "UNKNOWN" "V1" "D:/RONTEC/POWER/PCI/Altera/shift/db/shift.quartus_db" { Floorplan "D:/RONTEC/POWER/PCI/Altera/shift/" "" "" { clk } "NODE_NAME" } "" } } { "shift.bdf" "" { Schematic "D:/RONTEC/POWER/PCI/Altera/shift/shift.bdf" { { 248 368 536 264 "clk" "" } } } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.300 ns) 3.600 ns shiftout:inst\|bitcount\[1\] 2 REG LC8 11 " "Info: 2: + IC(0.000 ns) + CELL(1.300 ns) = 3.600 ns; Loc. = LC8; Fanout = 11; REG Node = 'shiftout:inst\|bitcount\[1\]'" { } { { "D:/RONTEC/POWER/PCI/Altera/shift/db/shift_cmp.qrpt" "" { Report "D:/RONTEC/POWER/PCI/Altera/shift/db/shift_cmp.qrpt" Compiler "shift" "UNKNOWN" "V1" "D:/RONTEC/POWER/PCI/Altera/shift/db/shift.quartus_db" { Floorplan "D:/RONTEC/POWER/PCI/Altera/shift/" "" "1.300 ns" { clk shiftout:inst|bitcount[1] } "NODE_NAME" } "" } } { "shiftout.v" "" { Text "D:/RONTEC/POWER/PCI/Altera/shift/shiftout.v" 61 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.600 ns 100.00 % " "Info: Total cell delay = 3.600 ns ( 100.00 % )" { } { } 0} } { { "D:/RONTEC/POWER/PCI/Altera/shift/db/shift_cmp.qrpt" "" { Report "D:/RONTEC/POWER/PCI/Altera/shift/db/shift_cmp.qrpt" Compiler "shift" "UNKNOWN" "V1" "D:/RONTEC/POWER/PCI/Altera/shift/db/shift.quartus_db" { Floorplan "D:/RONTEC/POWER/PCI/Altera/shift/" "" "3.600 ns" { clk shiftout:inst|bitcount[1] } "NODE_NAME" } "" } } { "e:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus42/bin/Technology_Viewer.qrui" "3.600 ns" { clk clk~out shiftout:inst|bitcount[1] } { 0.0ns 0.0ns 0.0ns } { 0.0ns 2.3ns 1.3ns } } } } 0} } { { "D:/RONTEC/POWER/PCI/Altera/shift/db/shift_cmp.qrpt" "" { Report "D:/RONTEC/POWER/PCI/Altera/shift/db/shift_cmp.qrpt" Compiler "shift" "UNKNOWN" "V1" "D:/RONTEC/POWER/PCI/Altera/shift/db/shift.quartus_db" { Floorplan "D:/RONTEC/POWER/PCI/Altera/shift/" "" "3.600 ns" { clk shiftout:inst|T_CLK } "NODE_NAME" } "" } } { "e:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus42/bin/Technology_Viewer.qrui" "3.600 ns" { clk clk~out shiftout:inst|T_CLK } { 0.0ns 0.0ns 0.0ns } { 0.0ns 2.3ns 1.3ns } } } { "D:/RONTEC/POWER/PCI/Altera/shift/db/shift_cmp.qrpt" "" { Report "D:/RONTEC/POWER/PCI/Altera/shift/db/shift_cmp.qrpt" Compiler "shift" "UNKNOWN" "V1" "D:/RONTEC/POWER/PCI/Altera/shift/db/shift.quartus_db" { Floorplan "D:/RONTEC/POWER/PCI/Altera/shift/" "" "3.600 ns" { clk shiftout:inst|bitcount[1] } "NODE_NAME" } "" } } { "e:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus42/bin/Technology_Viewer.qrui" "3.600 ns" { clk clk~out shiftout:inst|bitcount[1] } { 0.0ns 0.0ns 0.0ns } { 0.0ns 2.3ns 1.3ns } } } } 0} { "Info" "ITDB_FULL_TCO_DELAY" "1.600 ns - " "Info: - Micro clock to output delay of source is 1.600 ns" { } { { "shiftout.v" "" { Text "D:/RONTEC/POWER/PCI/Altera/shift/shiftout.v" 61 -1 0 } } } 0} { "Info" "ITDB_FULL_TH_DELAY" "1.300 ns + " "Info: + Micro hold delay of destination is 1.300 ns" { } { { "shiftout.v" "" { Text "D:/RONTEC/POWER/PCI/Altera/shift/shiftout.v" 11 -1 0 } } } 0} } { { "D:/RONTEC/POWER/PCI/Altera/shift/db/shift_cmp.qrpt" "" { Report "D:/RONTEC/POWER/PCI/Altera/shift/db/shift_cmp.qrpt" Compiler "shift" "UNKNOWN" "V1" "D:/RONTEC/POWER/PCI/Altera/shift/db/shift.quartus_db" { Floorplan "D:/RONTEC/POWER/PCI/Altera/shift/" "" "3.600 ns" { clk shiftout:inst|T_CLK } "NODE_NAME" } "" } } { "e:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus42/bin/Technology_Viewer.qrui" "3.600 ns" { clk clk~out shiftout:inst|T_CLK } { 0.0ns 0.0ns 0.0ns } { 0.0ns 2.3ns 1.3ns } } } { "D:/RONTEC/POWER/PCI/Altera/shift/db/shift_cmp.qrpt" "" { Report "D:/RONTEC/POWER/PCI/Altera/shift/db/shift_cmp.qrpt" Compiler "shift" "UNKNOWN" "V1" "D:/RONTEC/POWER/PCI/Altera/shift/db/shift.quartus_db" { Floorplan "D:/RONTEC/POWER/PCI/Altera/shift/" "" "3.600 ns" { clk shiftout:inst|bitcount[1] } "NODE_NAME" } "" } } { "e:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus42/bin/Technology_Viewer.qrui" "3.600 ns" { clk clk~out shiftout:inst|bitcount[1] } { 0.0ns 0.0ns 0.0ns } { 0.0ns 2.3ns 1.3ns } } } } 0} } { { "D:/RONTEC/POWER/PCI/Altera/shift/db/shift_cmp.qrpt" "" { Report "D:/RONTEC/POWER/PCI/Altera/shift/db/shift_cmp.qrpt" Compiler "shift" "UNKNOWN" "V1" "D:/RONTEC/POWER/PCI/Altera/shift/db/shift.quartus_db" { Floorplan "D:/RONTEC/POWER/PCI/Altera/shift/" "" "5.500 ns" { shiftout:inst|bitcount[1] shiftout:inst|T_CLK } "NODE_NAME" } "" } } { "e:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus42/bin/Technology_Viewer.qrui" "5.500 ns" { shiftout:inst|bitcount[1] shiftout:inst|T_CLK } { 0.0ns 2.3ns } { 0.0ns 3.2ns } } } { "D:/RONTEC/POWER/PCI/Altera/shift/db/shift_cmp.qrpt" "" { Report "D:/RONTEC/POWER/PCI/Altera/shift/db/shift_cmp.qrpt" Compiler "shift" "UNKNOWN" "V1" "D:/RONTEC/POWER/PCI/Altera/shift/db/shift.quartus_db" { Floorplan "D:/RONTEC/POWER/PCI/Altera/shift/" "" "3.600 ns" { clk shiftout:inst|T_CLK } "NODE_NAME" } "" } } { "e:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus42/bin/Technology_Viewer.qrui" "3.600 ns" { clk clk~out shiftout:inst|T_CLK } { 0.0ns 0.0ns 0.0ns } { 0.0ns 2.3ns 1.3ns } } } { "D:/RONTEC/POWER/PCI/Altera/shift/db/shift_cmp.qrpt" "" { Report "D:/RONTEC/POWER/PCI/Altera/shift/db/shift_cmp.qrpt" Compiler "shift" "UNKNOWN" "V1" "D:/RONTEC/POWER/PCI/Altera/shift/db/shift.quartus_db" { Floorplan "D:/RONTEC/POWER/PCI/Altera/shift/" "" "3.600 ns" { clk shiftout:inst|bitcount[1] } "NODE_NAME" } "" } } { "e:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus42/bin/Technology_Viewer.qrui" "3.600 ns" { clk clk~out shiftout:inst|bitcount[1] } { 0.0ns 0.0ns 0.0ns } { 0.0ns 2.3ns 1.3ns } } } } 0}
{ "Info" "ITDB_TSU_RESULT" "shiftout:inst\|rdy load clk 6.300 ns register " "Info: tsu for register \"shiftout:inst\|rdy\" (data pin = \"load\", clock pin = \"clk\") is 6.300 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "7.000 ns + Longest pin register " "Info: + Longest pin to register delay is 7.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.400 ns) 1.400 ns load 1 PIN PIN_34 21 " "Info: 1: + IC(0.000 ns) + CELL(1.400 ns) = 1.400 ns; Loc. = PIN_34; Fanout = 21; PIN Node = 'load'" { } { { "D:/RONTEC/POWER/PCI/Altera/shift/db/shift_cmp.qrpt" "" { Report "D:/RONTEC/POWER/PCI/Altera/shift/db/shift_cmp.qrpt" Compiler "shift" "UNKNOWN" "V1" "D:/RONTEC/POWER/PCI/Altera/shift/db/shift.quartus_db" { Floorplan "D:/RONTEC/POWER/PCI/Altera/shift/" "" "" { load } "NODE_NAME" } "" } } { "shift.bdf" "" { Schematic "D:/RONTEC/POWER/PCI/Altera/shift/shift.bdf" { { 216 368 536 232 "load" "" } } } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.400 ns) + CELL(3.200 ns) 7.000 ns shiftout:inst\|rdy 2 REG LC4 55 " "Info: 2: + IC(2.400 ns) + CELL(3.200 ns) = 7.000 ns; Loc. = LC4; Fanout = 55; REG Node = 'shiftout:inst\|rdy'" { } { { "D:/RONTEC/POWER/PCI/Altera/shift/db/shift_cmp.qrpt" "" { Report "D:/RONTEC/POWER/PCI/Altera/shift/db/shift_cmp.qrpt" Compiler "shift" "UNKNOWN" "V1" "D:/RONTEC/POWER/PCI/Altera/shift/db/shift.quartus_db" { Floorplan "D:/RONTEC/POWER/PCI/Altera/shift/" "" "5.600 ns" { load shiftout:inst|rdy } "NODE_NAME" } "" } } { "shiftout.v" "" { Text "D:/RONTEC/POWER/PCI/Altera/shift/shiftout.v" 10 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.600 ns 65.71 % " "Info: Total cell delay = 4.600 ns ( 65.71 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.400 ns 34.29 % " "Info: Total interconnect delay = 2.400 ns ( 34.29 % )" { } { } 0} } { { "D:/RONTEC/POWER/PCI/Altera/shift/db/shift_cmp.qrpt" "" { Report "D:/RONTEC/POWER/PCI/Altera/shift/db/shift_cmp.qrpt" Compiler "shift" "UNKNOWN" "V1" "D:/RONTEC/POWER/PCI/Altera/shift/db/shift.quartus_db" { Floorplan "D:/RONTEC/POWER/PCI/Altera/shift/" "" "7.000 ns" { load shiftout:inst|rdy } "NODE_NAME" } "" } } { "e:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus42/bin/Technology_Viewer.qrui" "7.000 ns" { load load~out shiftout:inst|rdy } { 0.000ns 0.000ns 2.400ns } { 0.000ns 1.400ns 3.200ns } } } } 0} { "Info" "ITDB_FULL_TSU_DELAY" "2.900 ns + " "Info: + Micro setup delay of destination is 2.900 ns" { } { { "shiftout.v" "" { Text "D:/RONTEC/POWER/PCI/Altera/shift/shiftout.v" 10 -1 0 } } } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 3.600 ns - Shortest register " "Info: - Shortest clock path from clock \"clk\" to destination register is 3.600 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.300 ns) 2.300 ns clk 1 CLK PIN_37 14 " "Info: 1: + IC(0.000 ns) + CELL(2.300 ns) = 2.300 ns; Loc. = PIN_37; Fanout = 14; CLK Node = 'clk'" { } { { "D:/RONTEC/POWER/PCI/Altera/shift/db/shift_cmp.qrpt" "" { Report "D:/RONTEC/POWER/PCI/Altera/shift/db/shift_cmp.qrpt" Compiler "shift" "UNKNOWN" "V1" "D:/RONTEC/POWER/PCI/Altera/shift/db/shift.quartus_db" { Floorplan "D:/RONTEC/POWER/PCI/Altera/shift/" "" "" { clk } "NODE_NAME" } "" } } { "shift.bdf" "" { Schematic "D:/RONTEC/POWER/PCI/Altera/shift/shift.bdf" { { 248 368 536 264 "clk" "" } } } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.300 ns) 3.600 ns shiftout:inst\|rdy 2 REG LC4 55 " "Info: 2: + IC(0.000 ns) + CELL(1.300 ns) = 3.600 ns; Loc. = LC4; Fanout = 55; REG Node = 'shiftout:inst\|rdy'" { } { { "D:/RONTEC/POWER/PCI/Altera/shift/db/shift_cmp.qrpt" "" { Report "D:/RONTEC/POWER/PCI/Altera/shift/db/shift_cmp.qrpt" Compiler "shift" "UNKNOWN" "V1" "D:/RONTEC/POWER/PCI/Altera/shift/db/shift.quartus_db" { Floorplan "D:/RONTEC/POWER/PCI/Altera/shift/" "" "1.300 ns" { clk shiftout:inst|rdy } "NODE_NAME" } "" } } { "shiftout.v" "" { Text "D:/RONTEC/POWER/PCI/Altera/shift/shiftout.v" 10 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.600 ns 100.00 % " "Info: Total cell delay = 3.600 ns ( 100.00 % )" { } { } 0} } { { "D:/RONTEC/POWER/PCI/Altera/shift/db/shift_cmp.qrpt" "" { Report "D:/RONTEC/POWER/PCI/Altera/shift/db/shift_cmp.qrpt" Compiler "shift" "UNKNOWN" "V1" "D:/RONTEC/POWER/PCI/Altera/shift/db/shift.quartus_db" { Floorplan "D:/RONTEC/POWER/PCI/Altera/shift/" "" "3.600 ns" { clk shiftout:inst|rdy } "NODE_NAME" } "" } } { "e:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus42/bin/Technology_Viewer.qrui" "3.600 ns" { clk clk~out shiftout:inst|rdy } { 0.000ns 0.000ns 0.000ns } { 0.000ns 2.300ns 1.300ns } } } } 0} } { { "D:/RONTEC/POWER/PCI/Altera/shift/db/shift_cmp.qrpt" "" { Report "D:/RONTEC/POWER/PCI/Altera/shift/db/shift_cmp.qrpt" Compiler "shift" "UNKNOWN" "V1" "D:/RONTEC/POWER/PCI/Altera/shift/db/shift.quartus_db" { Floorplan "D:/RONTEC/POWER/PCI/Altera/shift/" "" "7.000 ns" { load shiftout:inst|rdy } "NODE_NAME" } "" } } { "e:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus42/bin/Technology_Viewer.qrui" "7.000 ns" { load load~out shiftout:inst|rdy } { 0.000ns 0.000ns 2.400ns } { 0.000ns 1.400ns 3.200ns } } } { "D:/RONTEC/POWER/PCI/Altera/shift/db/shift_cmp.qrpt" "" { Report "D:/RONTEC/POWER/PCI/Altera/shift/db/shift_cmp.qrpt" Compiler "shift" "UNKNOWN" "V1" "D:/RONTEC/POWER/PCI/Altera/shift/db/shift.quartus_db" { Floorplan "D:/RONTEC/POWER/PCI/Altera/shift/" "" "3.600 ns" { clk shiftout:inst|rdy } "NODE_NAME" } "" } } { "e:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus42/bin/Technology_Viewer.qrui" "3.600 ns" { clk clk~out shiftout:inst|rdy } { 0.000ns 0.000ns 0.000ns } { 0.000ns 2.300ns 1.300ns } } } } 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk so shiftout:inst\|shifter\[0\] 13.800 ns register " "Info: tco from clock \"clk\" to destination pin \"so\" through register \"shiftout:inst\|shifter\[0\]\" is 13.800 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 3.600 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to source register is 3.600 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.300 ns) 2.300 ns clk 1 CLK PIN_37 14 " "Info: 1: + IC(0.000 ns) + CELL(2.300 ns) = 2.300 ns; Loc. = PIN_37; Fanout = 14; CLK Node = 'clk'" { } { { "D:/RONTEC/POWER/PCI/Altera/shift/db/shift_cmp.qrpt" "" { Report "D:/RONTEC/POWER/PCI/Altera/shift/db/shift_cmp.qrpt" Compiler "shift" "UNKNOWN" "V1" "D:/RONTEC/POWER/PCI/Altera/shift/db/shift.quartus_db" { Floorplan "D:/RONTEC/POWER/PCI/Altera/shift/" "" "" { clk } "NODE_NAME" } "" } } { "shift.bdf" "" { Schematic "D:/RONTEC/POWER/PCI/Altera/shift/shift.bdf" { { 248 368 536 264 "clk" "" } } } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.300 ns) 3.600 ns shiftout:inst\|shifter\[0\] 2 REG LC19 7 " "Info: 2: + IC(0.000 ns) + CELL(1.300 ns) = 3.600 ns; Loc. = LC19; Fanout = 7; REG Node = 'shiftout:inst\|shifter\[0\]'" { } { { "D:/RONTEC/POWER/PCI/Altera/shift/db/shift_cmp.qrpt" "" { Report "D:/RONTEC/POWER/PCI/Altera/shift/db/shift_cmp.qrpt" Compiler "shift" "UNKNOWN" "V1" "D:/RONTEC/POWER/PCI/Altera/shift/db/shift.quartus_db" { Floorplan "D:/RONTEC/POWER/PCI/Altera/shift/" "" "1.300 ns" { clk shiftout:inst|shifter[0] } "NODE_NAME" } "" } } { "shiftout.v" "" { Text "D:/RONTEC/POWER/PCI/Altera/shift/shiftout.v" 61 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.600 ns 100.00 % " "Info: Total cell delay = 3.600 ns ( 100.00 % )" { } { } 0} } { { "D:/RONTEC/POWER/PCI/Altera/shift/db/shift_cmp.qrpt" "" { Report "D:/RONTEC/POWER/PCI/Altera/shift/db/shift_cmp.qrpt" Compiler "shift" "UNKNOWN" "V1" "D:/RONTEC/POWER/PCI/Altera/shift/db/shift.quartus_db" { Floorplan "D:/RONTEC/POWER/PCI/Altera/shift/" "" "3.600 ns" { clk shiftout:inst|shifter[0] } "NODE_NAME" } "" } } { "e:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus42/bin/Technology_Viewer.qrui" "3.600 ns" { clk clk~out shiftout:inst|shifter[0] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 2.300ns 1.300ns } } } } 0} { "Info" "ITDB_FULL_TCO_DELAY" "1.600 ns + " "Info: + Micro clock to output delay of source is 1.600 ns" { } { { "shiftout.v" "" { Text "D:/RONTEC/POWER/PCI/Altera/shift/shiftout.v" 61 -1 0 } } } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "8.600 ns + Longest register pin " "Info: + Longest register to pin delay is 8.600 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns shiftout:inst\|shifter\[0\] 1 REG LC19 7 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC19; Fanout = 7; REG Node = 'shiftout:inst\|shifter\[0\]'" { } { { "D:/RONTEC/POWER/PCI/Altera/shift/db/shift_cmp.qrpt" "" { Report "D:/RONTEC/POWER/PCI/Altera/shift/db/shift_cmp.qrpt" Compiler "shift" "UNKNOWN" "V1" "D:/RONTEC/POWER/PCI/Altera/shift/db/shift.quartus_db" { Floorplan "D:/RONTEC/POWER/PCI/Altera/shift/" "" "" { shiftout:inst|shifter[0] } "NODE_NAME" } "" } } { "shiftout.v" "" { Text "D:/RONTEC/POWER/PCI/Altera/shift/shiftout.v" 61 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.300 ns) + CELL(4.500 ns) 6.800 ns shiftout:inst\|shifter\[0\]~292 2 COMB LC17 1 " "Info: 2: + IC(2.300 ns) + CELL(4.500 ns) = 6.800 ns; Loc. = LC17; Fanout = 1; COMB Node = 'shiftout:inst\|shifter\[0\]~292'" { } { { "D:/RONTEC/POWER/PCI/Altera/shift/db/shift_cmp.qrpt" "" { Report "D:/RONTEC/POWER/PCI/Altera/shift/db/shift_cmp.qrpt" Compiler "shift" "UNKNOWN" "V1" "D:/RONTEC/POWER/PCI/Altera/shift/db/shift.quartus_db" { Floorplan "D:/RONTEC/POWER/PCI/Altera/shift/" "" "6.800 ns" { shiftout:inst|shifter[0] shiftout:inst|shifter[0]~292 } "NODE_NAME" } "" } } { "shiftout.v" "" { Text "D:/RONTEC/POWER/PCI/Altera/shift/shiftout.v" 61 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.800 ns) 8.600 ns so 3 PIN PIN_15 0 " "Info: 3: + IC(0.000 ns) + CELL(1.800 ns) = 8.600 ns; Loc. = PIN_15; Fanout = 0; PIN Node = 'so'" { } { { "D:/RONTEC/POWER/PCI/Altera/shift/db/shift_cmp.qrpt" "" { Report "D:/RONTEC/POWER/PCI/Altera/shift/db/shift_cmp.qrpt" Compiler "shift" "UNKNOWN" "V1" "D:/RONTEC/POWER/PCI/Altera/shift/db/shift.quartus_db" { Floorplan "D:/RONTEC/POWER/PCI/Altera/shift/" "" "1.800 ns" { shiftout:inst|shifter[0]~292 so } "NODE_NAME" } "" } } { "shift.bdf" "" { Schematic "D:/RONTEC/POWER/PCI/Altera/shift/shift.bdf" { { 200 712 888 216 "so" "" } } } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "6.300 ns 73.26 % " "Info: Total cell delay = 6.300 ns ( 73.26 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.300 ns 26.74 % " "Info: Total interconnect delay = 2.300 ns ( 26.74 % )" { } { } 0} } { { "D:/RONTEC/POWER/PCI/Altera/shift/db/shift_cmp.qrpt" "" { Report "D:/RONTEC/POWER/PCI/Altera/shift/db/shift_cmp.qrpt" Compiler "shift" "UNKNOWN" "V1" "D:/RONTEC/POWER/PCI/Altera/shift/db/shift.quartus_db" { Floorplan "D:/RONTEC/POWER/PCI/Altera/shift/" "" "8.600 ns" { shiftout:inst|shifter[0] shiftout:inst|shifter[0]~292 so } "NODE_NAME" } "" } } { "e:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus42/bin/Technology_Viewer.qrui" "8.600 ns" { shiftout:inst|shifter[0] shiftout:inst|shifter[0]~292 so } { 0.000ns 2.300ns 0.000ns } { 0.000ns 4.500ns 1.800ns } } } } 0} } { { "D:/RONTEC/POWER/PCI/Altera/shift/db/shift_cmp.qrpt" "" { Report "D:/RONTEC/POWER/PCI/Altera/shift/db/shift_cmp.qrpt" Compiler "shift" "UNKNOWN" "V1" "D:/RONTEC/POWER/PCI/Altera/shift/db/shift.quartus_db" { Floorplan "D:/RONTEC/POWER/PCI/Altera/shift/" "" "3.600 ns" { clk shiftout:inst|shifter[0] } "NODE_NAME" } "" } } { "e:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus42/bin/Technology_Viewer.qrui" "3.600 ns" { clk clk~out shiftout:inst|shifter[0] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 2.300ns 1.300ns } } } { "D:/RONTEC/POWER/PCI/Altera/shift/db/shift_cmp.qrpt" "" { Report "D:/RONTEC/POWER/PCI/Altera/shift/db/shift_cmp.qrpt" Compiler "shift" "UNKNOWN" "V1" "D:/RONTEC/POWER/PCI/Altera/shift/db/shift.quartus_db" { Floorplan "D:/RONTEC/POWER/PCI/Altera/shift/" "" "8.600 ns" { shiftout:inst|shifter[0] shiftout:inst|shifter[0]~292 so } "NODE_NAME" } "" } } { "e:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus42/bin/Technology_Viewer.qrui" "8.600 ns" { shiftout:inst|shifter[0] shiftout:inst|shifter[0]~292 so } { 0.000ns 2.300ns 0.000ns } { 0.000ns 4.500ns 1.800ns } } } } 0}
{ "Info" "ITDB_TH_RESULT" "shiftout:inst\|shifter\[0\] din\[0\] clk -2.000 ns register " "Info: th for register \"shiftout:inst\|shifter\[0\]\" (data pin = \"din\[0\]\", clock pin = \"clk\") is -2.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 3.600 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to destination register is 3.600 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.300 ns) 2.300 ns clk 1 CLK PIN_37 14 " "Info: 1: + IC(0.000 ns) + CELL(2.300 ns) = 2.300 ns; Loc. = PIN_37; Fanout = 14; CLK Node = 'clk'" { } { { "D:/RONTEC/POWER/PCI/Altera/shift/db/shift_cmp.qrpt" "" { Report "D:/RONTEC/POWER/PCI/Altera/shift/db/shift_cmp.qrpt" Compiler "shift" "UNKNOWN" "V1" "D:/RONTEC/POWER/PCI/Altera/shift/db/shift.quartus_db" { Floorplan "D:/RONTEC/POWER/PCI/Altera/shift/" "" "" { clk } "NODE_NAME" } "" } } { "shift.bdf" "" { Schematic "D:/RONTEC/POWER/PCI/Altera/shift/shift.bdf" { { 248 368 536 264 "clk" "" } } } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.300 ns) 3.600 ns shiftout:inst\|shifter\[0\] 2 REG LC19 7 " "Info: 2: + IC(0.000 ns) + CELL(1.300 ns) = 3.600 ns; Loc. = LC19; Fanout = 7; REG Node = 'shiftout:inst\|shifter\[0\]'" { } { { "D:/RONTEC/POWER/PCI/Altera/shift/db/shift_cmp.qrpt" "" { Report "D:/RONTEC/POWER/PCI/Altera/shift/db/shift_cmp.qrpt" Compiler "shift" "UNKNOWN" "V1" "D:/RONTEC/POWER/PCI/Altera/shift/db/shift.quartus_db" { Floorplan "D:/RONTEC/POWER/PCI/Altera/shift/" "" "1.300 ns" { clk shiftout:inst|shifter[0] } "NODE_NAME" } "" } } { "shiftout.v" "" { Text "D:/RONTEC/POWER/PCI/Altera/shift/shiftout.v" 61 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.600 ns 100.00 % " "Info: Total cell delay = 3.600 ns ( 100.00 % )" { } { } 0} } { { "D:/RONTEC/POWER/PCI/Altera/shift/db/shift_cmp.qrpt" "" { Report "D:/RONTEC/POWER/PCI/Altera/shift/db/shift_cmp.qrpt" Compiler "shift" "UNKNOWN" "V1" "D:/RONTEC/POWER/PCI/Altera/shift/db/shift.quartus_db" { Floorplan "D:/RONTEC/POWER/PCI/Altera/shift/" "" "3.600 ns" { clk shiftout:inst|shifter[0] } "NODE_NAME" } "" } } { "e:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus42/bin/Technology_Viewer.qrui" "3.600 ns" { clk clk~out shiftout:inst|shifter[0] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 2.300ns 1.300ns } } } } 0} { "Info" "ITDB_FULL_TH_DELAY" "1.300 ns + " "Info: + Micro hold delay of destination is 1.300 ns" { } { { "shiftout.v" "" { Text "D:/RONTEC/POWER/PCI/Altera/shift/shiftout.v" 61 -1 0 } } } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.900 ns - Shortest pin register " "Info: - Shortest pin to register delay is 6.900 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.400 ns) 1.400 ns din\[0\] 1 PIN PIN_22 2 " "Info: 1: + IC(0.000 ns) + CELL(1.400 ns) = 1.400 ns; Loc. = PIN_22; Fanout = 2; PIN Node = 'din\[0\]'" { } { { "D:/RONTEC/POWER/PCI/Altera/shift/db/shift_cmp.qrpt" "" { Report "D:/RONTEC/POWER/PCI/Altera/shift/db/shift_cmp.qrpt" Compiler "shift" "UNKNOWN" "V1" "D:/RONTEC/POWER/PCI/Altera/shift/db/shift.quartus_db" { Floorplan "D:/RONTEC/POWER/PCI/Altera/shift/" "" "" { din[0] } "NODE_NAME" } "" } } { "shift.bdf" "" { Schematic "D:/RONTEC/POWER/PCI/Altera/shift/shift.bdf" { { 184 368 536 200 "din\[7..0\]" "" } } } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.300 ns) + CELL(3.200 ns) 6.900 ns shiftout:inst\|shifter\[0\] 2 REG LC19 7 " "Info: 2: + IC(2.300 ns) + CELL(3.200 ns) = 6.900 ns; Loc. = LC19; Fanout = 7; REG Node = 'shiftout:inst\|shifter\[0\]'" { } { { "D:/RONTEC/POWER/PCI/Altera/shift/db/shift_cmp.qrpt" "" { Report "D:/RONTEC/POWER/PCI/Altera/shift/db/shift_cmp.qrpt" Compiler "shift" "UNKNOWN" "V1" "D:/RONTEC/POWER/PCI/Altera/shift/db/shift.quartus_db" { Floorplan "D:/RONTEC/POWER/PCI/Altera/shift/" "" "5.500 ns" { din[0] shiftout:inst|shifter[0] } "NODE_NAME" } "" } } { "shiftout.v" "" { Text "D:/RONTEC/POWER/PCI/Altera/shift/shiftout.v" 61 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.600 ns 66.67 % " "Info: Total cell delay = 4.600 ns ( 66.67 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.300 ns 33.33 % " "Info: Total interconnect delay = 2.300 ns ( 33.33 % )" { } { } 0} } { { "D:/RONTEC/POWER/PCI/Altera/shift/db/shift_cmp.qrpt" "" { Report "D:/RONTEC/POWER/PCI/Altera/shift/db/shift_cmp.qrpt" Compiler "shift" "UNKNOWN" "V1" "D:/RONTEC/POWER/PCI/Altera/shift/db/shift.quartus_db" { Floorplan "D:/RONTEC/POWER/PCI/Altera/shift/" "" "6.900 ns" { din[0] shiftout:inst|shifter[0] } "NODE_NAME" } "" } } { "e:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus42/bin/Technology_Viewer.qrui" "6.900 ns" { din[0] din[0]~out shiftout:inst|shifter[0] } { 0.000ns 0.000ns 2.300ns } { 0.000ns 1.400ns 3.200ns } } } } 0} } { { "D:/RONTEC/POWER/PCI/Altera/shift/db/shift_cmp.qrpt" "" { Report "D:/RONTEC/POWER/PCI/Altera/shift/db/shift_cmp.qrpt" Compiler "shift" "UNKNOWN" "V1" "D:/RONTEC/POWER/PCI/Altera/shift/db/shift.quartus_db" { Floorplan "D:/RONTEC/POWER/PCI/Altera/shift/" "" "3.600 ns" { clk shiftout:inst|shifter[0] } "NODE_NAME" } "" } } { "e:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus42/bin/Technology_Viewer.qrui" "3.600 ns" { clk clk~out shiftout:inst|shifter[0] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 2.300ns 1.300ns } } } { "D:/RONTEC/POWER/PCI/Altera/shift/db/shift_cmp.qrpt" "" { Report "D:/RONTEC/POWER/PCI/Altera/shift/db/shift_cmp.qrpt" Compiler "shift" "UNKNOWN" "V1" "D:/RONTEC/POWER/PCI/Altera/shift/db/shift.quartus_db" { Floorplan "D:/RONTEC/POWER/PCI/Altera/shift/" "" "6.900 ns" { din[0] shiftout:inst|shifter[0] } "NODE_NAME" } "" } } { "e:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus42/bin/Technology_Viewer.qrui" "6.900 ns" { din[0] din[0]~out shiftout:inst|shifter[0] } { 0.000ns 0.000ns 2.300ns } { 0.000ns 1.400ns 3.200ns } } } } 0}
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