shift.fit.eqn

用verilog编写的USB下载线程序 实现USB协议和JTAG接口的数据转换实现状态机。

--B1_T_CLK is shiftout:inst|T_CLK at LC3
B1_T_CLK_p0_out = !reset & !B1_rdy & !B1_T_CLK & B1_bitcount[0];
B1_T_CLK_p1_out = !reset & B1_rdy & B1_T_CLK;
B1_T_CLK_p2_out = !reset & !B1_rdy & !B1_T_CLK & B1_bitcount[3];
B1_T_CLK_p3_out = !reset & !B1_rdy & !B1_T_CLK & B1_bitcount[2];
B1_T_CLK_p4_out = !reset & !B1_rdy & !B1_T_CLK & B1_bitcount[1];
B1_T_CLK_or_out = B1_T_CLK_p0_out # B1_T_CLK_p1_out # B1_T_CLK_p2_out # B1_T_CLK_p3_out # B1_T_CLK_p4_out;
B1_T_CLK_reg_input = B1_T_CLK_or_out;
B1_T_CLK = DFFE(B1_T_CLK_reg_input, GLOBAL(clk), , , );


--B1_bitcount[0] is shiftout:inst|bitcount[0] at LC9
B1_bitcount[0]_p0_out = B1_rdy & !reset & B1_bitcount[0] & !load;
B1_bitcount[0]_p1_out = B1_bitcount[3] & !B1_rdy & !B1_T_CLK & !reset & !B1_bitcount[0];
B1_bitcount[0]_p2_out = !B1_rdy & !B1_T_CLK & !reset & !B1_bitcount[0] & B1_bitcount[2];
B1_bitcount[0]_p3_out = !B1_rdy & !B1_T_CLK & !reset & !B1_bitcount[0] & B1_bitcount[1];
B1_bitcount[0]_p4_out = !B1_rdy & B1_T_CLK & !reset & B1_bitcount[0];
B1_bitcount[0]_or_out = B1_bitcount[0]_p0_out # B1_bitcount[0]_p1_out # B1_bitcount[0]_p2_out # B1_bitcount[0]_p3_out # B1_bitcount[0]_p4_out;
B1_bitcount[0]_reg_input = B1_bitcount[0]_or_out;
B1_bitcount[0] = DFFE(B1_bitcount[0]_reg_input, GLOBAL(clk), , , );


--B1_bitcount[1] is shiftout:inst|bitcount[1] at LC8
B1_bitcount[1]_p0_out = B1_rdy & !reset & B1_bitcount[1] & !load;
B1_bitcount[1]_p1_out = B1_bitcount[3] & !B1_bitcount[0] & !B1_rdy & !B1_T_CLK & !reset & !B1_bitcount[1];
B1_bitcount[1]_p2_out = !B1_bitcount[0] & !B1_rdy & !B1_T_CLK & !reset & !B1_bitcount[1] & B1_bitcount[2];
B1_bitcount[1]_p3_out = B1_bitcount[0] & !B1_rdy & !reset & B1_bitcount[1];
B1_bitcount[1]_p4_out = !B1_rdy & B1_T_CLK & !reset & B1_bitcount[1];
B1_bitcount[1]_or_out = B1_bitcount[1]_p0_out # B1_bitcount[1]_p1_out # B1_bitcount[1]_p2_out # B1_bitcount[1]_p3_out # B1_bitcount[1]_p4_out;
B1_bitcount[1]_reg_input = B1_bitcount[1]_or_out;
B1_bitcount[1] = DFFE(B1_bitcount[1]_reg_input, GLOBAL(clk), , , );


--B1_bitcount[2] is shiftout:inst|bitcount[2] at LC7
B1_bitcount[2]_p1_out = B1_bitcount[3] & !reset & !B1_rdy & !B1_T_CLK & !B1_bitcount[0] & !B1_bitcount[1];
B1_bitcount[2]_p2_out = B1_rdy & load & B1_bitcount[2];
B1_bitcount[2]_p3_out = reset & B1_bitcount[2];
B1_bitcount[2]_p4_out = !B1_rdy & !B1_T_CLK & !B1_bitcount[0] & !B1_bitcount[1] & B1_bitcount[2];
B1_bitcount[2]_or_out = B1_bitcount[2]_p1_out # B1_bitcount[2]_p2_out # B1_bitcount[2]_p3_out # B1_bitcount[2]_p4_out;
B1_bitcount[2]_reg_input = B1_bitcount[2]_or_out;
B1_bitcount[2] = TFFE(B1_bitcount[2]_reg_input, GLOBAL(clk), , , );


--B1_bitcount[3] is shiftout:inst|bitcount[3] at LC2
B1_bitcount[3]_p1_out = load & B1_rdy & !reset & !B1_bitcount[3];
B1_bitcount[3]_p2_out = !B1_rdy & B1_bitcount[3] & !B1_bitcount[2] & !B1_bitcount[1] & !B1_bitcount[0] & !B1_T_CLK;
B1_bitcount[3]_p3_out = reset & B1_bitcount[3];
B1_bitcount[3]_or_out = B1_bitcount[3]_p1_out # B1_bitcount[3]_p2_out # B1_bitcount[3]_p3_out;
B1_bitcount[3]_reg_input = B1_bitcount[3]_or_out;
B1_bitcount[3] = TFFE(B1_bitcount[3]_reg_input, GLOBAL(clk), , , );


--B1_rdy is shiftout:inst|rdy at LC4
B1_rdy_p1_out = !load & B1_rdy;
B1_rdy_p2_out = !B1_rdy & !B1_T_CLK & !B1_bitcount[3] & !B1_bitcount[2] & !B1_bitcount[1] & !B1_bitcount[0];
B1_rdy_or_out = B1_rdy_p1_out # B1_rdy_p2_out # reset;
B1_rdy_reg_input = B1_rdy_or_out;
B1_rdy = DFFE(B1_rdy_reg_input, GLOBAL(clk), , , );


--B1_shifter[7] is shiftout:inst|shifter[7] at LC11
B1_shifter[7]_p1_out = si & B1_T_CLK & !B1_rdy & !reset & !B1_shifter[7];
B1_shifter[7]_p2_out = B1_rdy & !reset & !B1_shifter[7] & din[7] & load;
B1_shifter[7]_p3_out = !si & B1_T_CLK & !B1_rdy & !reset & B1_shifter[7];
B1_shifter[7]_p4_out = B1_rdy & !reset & B1_shifter[7] & !din[7] & load;
B1_shifter[7]_or_out = B1_shifter[7]_p1_out # B1_shifter[7]_p2_out # B1_shifter[7]_p3_out # B1_shifter[7]_p4_out;
B1_shifter[7]_reg_input = B1_shifter[7]_or_out;
B1_shifter[7] = TFFE(B1_shifter[7]_reg_input, GLOBAL(clk), , , );


--B1_shifter[6] is shiftout:inst|shifter[6] at LC14
B1_shifter[6]_p1_out = B1_shifter[7] & B1_T_CLK & !B1_rdy & !reset & !B1_shifter[6];
B1_shifter[6]_p2_out = B1_rdy & !reset & !B1_shifter[6] & din[6] & load;
B1_shifter[6]_p3_out = !B1_shifter[7] & B1_T_CLK & !B1_rdy & !reset & B1_shifter[6];
B1_shifter[6]_p4_out = B1_rdy & !reset & B1_shifter[6] & !din[6] & load;
B1_shifter[6]_or_out = B1_shifter[6]_p1_out # B1_shifter[6]_p2_out # B1_shifter[6]_p3_out # B1_shifter[6]_p4_out;
B1_shifter[6]_reg_input = B1_shifter[6]_or_out;
B1_shifter[6] = TFFE(B1_shifter[6]_reg_input, GLOBAL(clk), , , );


--B1_shifter[5] is shiftout:inst|shifter[5] at LC5
B1_shifter[5]_p1_out = B1_shifter[6] & B1_T_CLK & !B1_rdy & !reset & !B1_shifter[5];
B1_shifter[5]_p2_out = B1_rdy & !reset & !B1_shifter[5] & din[5] & load;
B1_shifter[5]_p3_out = !B1_shifter[6] & B1_T_CLK & !B1_rdy & !reset & B1_shifter[5];
B1_shifter[5]_p4_out = B1_rdy & !reset & B1_shifter[5] & !din[5] & load;
B1_shifter[5]_or_out = B1_shifter[5]_p1_out # B1_shifter[5]_p2_out # B1_shifter[5]_p3_out # B1_shifter[5]_p4_out;
B1_shifter[5]_reg_input = B1_shifter[5]_or_out;
B1_shifter[5] = TFFE(B1_shifter[5]_reg_input, GLOBAL(clk), , , );


--B1_shifter[4] is shiftout:inst|shifter[4] at LC16
B1_shifter[4]_p1_out = B1_shifter[5] & B1_T_CLK & !B1_rdy & !reset & !B1_shifter[4];
B1_shifter[4]_p2_out = B1_rdy & !reset & !B1_shifter[4] & din[4] & load;
B1_shifter[4]_p3_out = !B1_shifter[5] & B1_T_CLK & !B1_rdy & !reset & B1_shifter[4];
B1_shifter[4]_p4_out = B1_rdy & !reset & B1_shifter[4] & !din[4] & load;
B1_shifter[4]_or_out = B1_shifter[4]_p1_out # B1_shifter[4]_p2_out # B1_shifter[4]_p3_out # B1_shifter[4]_p4_out;
B1_shifter[4]_reg_input = B1_shifter[4]_or_out;
B1_shifter[4] = TFFE(B1_shifter[4]_reg_input, GLOBAL(clk), , , );


--B1_shifter[3] is shiftout:inst|shifter[3] at LC1
B1_shifter[3]_p1_out = B1_shifter[4] & B1_T_CLK & !B1_rdy & !reset & !B1_shifter[3];
B1_shifter[3]_p2_out = B1_rdy & !reset & !B1_shifter[3] & din[3] & load;
B1_shifter[3]_p3_out = !B1_shifter[4] & B1_T_CLK & !B1_rdy & !reset & B1_shifter[3];
B1_shifter[3]_p4_out = B1_rdy & !reset & B1_shifter[3] & !din[3] & load;
B1_shifter[3]_or_out = B1_shifter[3]_p1_out # B1_shifter[3]_p2_out # B1_shifter[3]_p3_out # B1_shifter[3]_p4_out;
B1_shifter[3]_reg_input = B1_shifter[3]_or_out;
B1_shifter[3] = TFFE(B1_shifter[3]_reg_input, GLOBAL(clk), , , );


--B1_shifter[2] is shiftout:inst|shifter[2] at LC21
B1_shifter[2]_p1_out = B1_shifter[3] & B1_T_CLK & !B1_rdy & !reset & !B1_shifter[2];
B1_shifter[2]_p2_out = B1_rdy & !reset & !B1_shifter[2] & din[2] & load;
B1_shifter[2]_p3_out = !B1_shifter[3] & B1_T_CLK & !B1_rdy & !reset & B1_shifter[2];
B1_shifter[2]_p4_out = B1_rdy & !reset & B1_shifter[2] & !din[2] & load;
B1_shifter[2]_or_out = B1_shifter[2]_p1_out # B1_shifter[2]_p2_out # B1_shifter[2]_p3_out # B1_shifter[2]_p4_out;
B1_shifter[2]_reg_input = B1_shifter[2]_or_out;
B1_shifter[2] = TFFE(B1_shifter[2]_reg_input, GLOBAL(clk), , , );


--B1_shifter[1] is shiftout:inst|shifter[1] at LC20
B1_shifter[1]_p1_out = B1_shifter[2] & B1_T_CLK & !B1_rdy & !reset & !B1_shifter[1];
B1_shifter[1]_p2_out = B1_rdy & !reset & !B1_shifter[1] & din[1] & load;
B1_shifter[1]_p3_out = !B1_shifter[2] & B1_T_CLK & !B1_rdy & !reset & B1_shifter[1];
B1_shifter[1]_p4_out = B1_rdy & !reset & B1_shifter[1] & !din[1] & load;
B1_shifter[1]_or_out = B1_shifter[1]_p1_out # B1_shifter[1]_p2_out # B1_shifter[1]_p3_out # B1_shifter[1]_p4_out;
B1_shifter[1]_reg_input = B1_shifter[1]_or_out;
B1_shifter[1] = TFFE(B1_shifter[1]_reg_input, GLOBAL(clk), , , );


--B1_shifter[0] is shiftout:inst|shifter[0] at LC19
B1_shifter[0]_p1_out = B1_shifter[1] & B1_T_CLK & !B1_rdy & !reset & !B1_shifter[0];
B1_shifter[0]_p2_out = B1_rdy & !reset & !B1_shifter[0] & din[0] & load;
B1_shifter[0]_p3_out = !B1_shifter[1] & B1_T_CLK & !B1_rdy & !reset & B1_shifter[0];
B1_shifter[0]_p4_out = B1_rdy & !reset & B1_shifter[0] & !din[0] & load;
B1_shifter[0]_or_out = B1_shifter[0]_p1_out # B1_shifter[0]_p2_out # B1_shifter[0]_p3_out # B1_shifter[0]_p4_out;
B1_shifter[0]_reg_input = B1_shifter[0]_or_out;
B1_shifter[0] = TFFE(B1_shifter[0]_reg_input, GLOBAL(clk), , , );


--B1L01 is shiftout:inst|shifter[0]~292 at LC17
B1L01_or_out = B1_shifter[0];
B1L01 = B1L01_or_out;


--si is si at PIN_28
--operation mode is input

si = INPUT();


--load is load at PIN_34
--operation mode is input

load = INPUT();


--reset is reset at PIN_35
--operation mode is input

reset = INPUT();


--clk is clk at PIN_37
--operation mode is input

clk = INPUT();


--din[7] is din[7] at PIN_19
--operation mode is input

din[7] = INPUT();


--din[6] is din[6] at PIN_40
--operation mode is input

din[6] = INPUT();


--din[5] is din[5] at PIN_21
--operation mode is input

din[5] = INPUT();


--din[4] is din[4] at PIN_31
--operation mode is input

din[4] = INPUT();


--din[3] is din[3] at PIN_10
--operation mode is input

din[3] = INPUT();


--din[2] is din[2] at PIN_23
--operation mode is input

din[2] = INPUT();


--din[1] is din[1] at PIN_25
--operation mode is input

din[1] = INPUT();


--din[0] is din[0] at PIN_22
--operation mode is input

din[0] = INPUT();


--T_CLK is T_CLK at PIN_5
--operation mode is output

T_CLK = OUTPUT(B1_T_CLK);


--rdy is rdy at PIN_3
--operation mode is output

rdy = OUTPUT(B1_rdy);


--dout[7] is dout[7] at PIN_44
--operation mode is output

dout[7] = OUTPUT(B1_shifter[7]);


--dout[6] is dout[6] at PIN_43
--operation mode is output

dout[6] = OUTPUT(B1_shifter[6]);


--dout[5] is dout[5] at PIN_2
--operation mode is output

dout[5] = OUTPUT(B1_shifter[5]);


--dout[4] is dout[4] at PIN_42
--operation mode is output

dout[4] = OUTPUT(B1_shifter[4]);


--dout[3] is dout[3] at PIN_6
--operation mode is output

dout[3] = OUTPUT(B1_shifter[3]);


--dout[2] is dout[2] at PIN_12
--operation mode is output

dout[2] = OUTPUT(B1_shifter[2]);


--dout[1] is dout[1] at PIN_13
--operation mode is output

dout[1] = OUTPUT(B1_shifter[1]);


--dout[0] is dout[0] at PIN_14
--operation mode is output

dout[0] = OUTPUT(B1_shifter[0]);


--so is so at PIN_15
--operation mode is output

so = OUTPUT(B1L01);