testlatch.tan.rpt

用verilog编写的USB下载线程序 实现USB协议和JTAG接口的数据转换实现状态机。

Timing Analyzer report for testlatch
Tue Dec 13 17:38:38 2005
Version 4.2 Build 157 12/07/2004 SJ Full Version


---------------------
; Table of Contents ;
---------------------
  1. Legal Notice
  2. Timing Analyzer Summary
  3. Timing Analyzer Settings
  4. Clock Settings Summary
  5. Clock Setup: 'CLK'
  6. Clock Hold: 'CLK'
  7. tsu
  8. tco
  9. tpd
 10. th
 11. Timing Analyzer Messages



----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2004 Altera Corporation
Any  megafunction  design,  and related netlist (encrypted  or  decrypted),
support information,  device programming or simulation file,  and any other
associated  documentation or information  provided by  Altera  or a partner
under  Altera's   Megafunction   Partnership   Program  may  be  used  only
to program  PLD  devices (but not masked  PLD  devices) from  Altera.   Any
other  use  of such  megafunction  design,  netlist,  support  information,
device programming or simulation file,  or any other  related documentation
or information  is prohibited  for  any  other purpose,  including, but not
limited to  modification,  reverse engineering,  de-compiling, or use  with
any other  silicon devices,  unless such use is  explicitly  licensed under
a separate agreement with  Altera  or a megafunction partner.  Title to the
intellectual property,  including patents,  copyrights,  trademarks,  trade
secrets,  or maskworks,  embodied in any such megafunction design, netlist,
support  information,  device programming or simulation file,  or any other
related documentation or information provided by  Altera  or a megafunction
partner, remains with Altera, the megafunction partner, or their respective
licensors. No other licenses, including any licenses needed under any third
party's intellectual property, are provided herein.



+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Summary                                                                                                                                                                                                     ;
+------------------------------+-----------+----------------------------------+----------------------------------+--------------------------------------------+------------------------+------------+----------+--------------+
; Type                         ; Slack     ; Required Time                    ; Actual Time                      ; From                                       ; To                     ; From Clock ; To Clock ; Failed Paths ;
+------------------------------+-----------+----------------------------------+----------------------------------+--------------------------------------------+------------------------+------------+----------+--------------+
; Worst-case tsu               ; N/A       ; None                             ; 7.200 ns                         ; D[7]                                       ; JTAGcore:inst4|SM~125  ;            ; CLK      ; 0            ;
; Worst-case tco               ; N/A       ; None                             ; 14.000 ns                        ; JTAGcore:inst4|shiftout:shifter|shifter[0] ; ASDI                   ; CLK        ;          ; 0            ;
; Worst-case tpd               ; N/A       ; None                             ; 10.100 ns                        ; CDONE                                      ; D[0]                   ;            ;          ; 0            ;
; Worst-case th                ; N/A       ; None                             ; -0.100 ns                        ; D[7]                                       ; JTAGcore:inst4|RED_LED ;            ; CLK      ; 0            ;
; Clock Setup: 'CLK'           ; 28.900 ns ; 25.00 MHz ( period = 40.000 ns ) ; 90.09 MHz ( period = 11.100 ns ) ; JTAGcore:inst4|SM~125                      ; JTAGcore:inst4|SM~127  ; CLK        ; CLK      ; 0            ;
; Clock Hold: 'CLK'            ; 4.000 ns  ; 25.00 MHz ( period = 40.000 ns ) ; N/A                              ; JTAGcore:inst4|SM~126                      ; JTAGcore:inst4|direct  ; CLK        ; CLK      ; 0            ;
; Total number of failed paths ;           ;                                  ;                                  ;                                            ;                        ;            ;          ; 0            ;