testlatch.qsf

用verilog编写的USB下载线程序 实现USB协议和JTAG接口的数据转换实现状态机。

# Copyright (C) 1991-2004 Altera Corporation
# Any  megafunction  design,  and related netlist (encrypted  or  decrypted),
# support information,  device programming or simulation file,  and any other
# associated  documentation or information  provided by  Altera  or a partner
# under  Altera's   Megafunction   Partnership   Program  may  be  used  only
# to program  PLD  devices (but not masked  PLD  devices) from  Altera.   Any
# other  use  of such  megafunction  design,  netlist,  support  information,
# device programming or simulation file,  or any other  related documentation
# or information  is prohibited  for  any  other purpose,  including, but not
# limited to  modification,  reverse engineering,  de-compiling, or use  with
# any other  silicon devices,  unless such use is  explicitly  licensed under
# a separate agreement with  Altera  or a megafunction partner.  Title to the
# intellectual property,  including patents,  copyrights,  trademarks,  trade
# secrets,  or maskworks,  embodied in any such megafunction design, netlist,
# support  information,  device programming or simulation file,  or any other
# related documentation or information provided by  Altera  or a megafunction
# partner, remains with Altera, the megafunction partner, or their respective
# licensors. No other licenses, including any licenses needed under any third
# party's intellectual property, are provided herein.


# The default values for assignments are stored in the file
#		testlatch_assignment_defaults.qdf
# If this file doesn't exist, and for assignments not listed, see file
#		assignment_defaults.qdf

# Altera recommends that you do not modify this file. This
# file is updated automatically by the Quartus II software
# and any changes you make may be lost or overwritten.


# Project-Wide Assignments
# ========================
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 4.2
set_global_assignment -name PROJECT_CREATION_TIME_DATE "11:11:47  OCTOBER 30, 2005"
set_global_assignment -name LAST_QUARTUS_VERSION 4.2
set_global_assignment -name BDF_FILE "D:\\RONTEC\\POWER\\PCI\\Altera\\testlatch.bdf"
set_global_assignment -name VERILOG_FILE JtagCore.V

# Pin & Location Assignments
# ==========================
set_location_assignment PIN_40 -to CLK
set_location_assignment PIN_33 -to GREEN_LED
set_location_assignment PIN_34 -to RED_LED
set_location_assignment PIN_14 -to N_RD
set_location_assignment PIN_15 -to WR
set_location_assignment PIN_19 -to N_RXF
set_location_assignment PIN_18 -to N_TXE
set_location_assignment PIN_39 -to CFG0
set_location_assignment PIN_38 -to CFG1
set_location_assignment PIN_37 -to CFG2
set_location_assignment PIN_35 -to CFG3
set_location_assignment PIN_31 -to JTCK
set_location_assignment PIN_25 -to N_CE
set_location_assignment PIN_27 -to N_CONF
set_location_assignment PIN_22 -to N_CS
set_location_assignment PIN_21 -to ASDI
set_location_assignment PIN_23 -to DATAOUT
set_location_assignment PIN_28 -to CDONE
set_location_assignment PIN_20 -to N_PWREN
set_location_assignment PIN_44 -to PIN_44_OUT
set_location_assignment PIN_2 -to D[0]
set_location_assignment PIN_3 -to D[1]
set_location_assignment PIN_5 -to D[2]
set_location_assignment PIN_6 -to D[3]
set_location_assignment PIN_8 -to D[4]
set_location_assignment PIN_10 -to D[5]
set_location_assignment PIN_12 -to D[6]
set_location_assignment PIN_13 -to D[7]

# Timing Assignments
# ==================
set_global_assignment -name IGNORE_CLOCK_SETTINGS OFF
set_global_assignment -name FMAX_REQUIREMENT "25.0 MHz"

# Analysis & Synthesis Assignments
# ================================
set_global_assignment -name DEVICE_FILTER_PIN_COUNT 44
set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 10
set_global_assignment -name FAMILY MAX3000A
set_global_assignment -name TOP_LEVEL_ENTITY testlatch

# Fitter Assignments
# ==================
set_global_assignment -name DEVICE "EPM3064ATC44-10"
set_global_assignment -name OPTIMIZE_HOLD_TIMING OFF
set_global_assignment -name FITTER_EFFORT "STANDARD FIT"
set_global_assignment -name MAX7000_DEVICE_IO_STANDARD LVTTL

# Assembler Assignments
# =====================
set_global_assignment -name MAX7000_USE_CHECKSUM_AS_USERCODE ON
set_global_assignment -name RESERVE_ALL_UNUSED_PINS_NO_OUTPUT_GND "AS INPUT TRI-STATED"

# Simulator Assignments
# =====================
set_global_assignment -name GLITCH_INTERVAL 1
set_global_assignment -name SIMULATOR_GENERATE_SIGNAL_ACTIVITY_FILE OFF

# --------------------
# start CLOCK(mainclk)

	# Timing Assignments
	# ==================
	set_global_assignment -name FMAX_REQUIREMENT "25.0 MHz" -section_id mainclk

# end CLOCK(mainclk)
# ------------------

# -----------------------
# start ENTITY(testlatch)

	# Timing Assignments
	# ==================
	set_instance_assignment -name CLOCK_SETTINGS mainclk -to CLK

# end ENTITY(testlatch)
# ---------------------