clk_5div.vhd

应用VHDL语言将高稳晶振分频得到1pps

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-- Company: 
-- Engineer:
--
-- Create Date:    16:25:08 09/09/07
-- Design Name:    
-- Module Name:    clk_5div - Behavioral
-- Project Name:   
-- Target Device:  
-- Tool versions:  
-- Description:
--
-- Dependencies:
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
-- 
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity clk_5div is  
  port(clk:in std_logic;
        clk_div5:out std_logic);
end clk_5div;

architecture Behavioral of clk_5div is
    constant ld:std_logic_vector(2 downto 0):="010";
    constant md:std_logic_vector(2 downto 0):="100";
    constant zero:std_logic_vector(2 downto 0):=(others=>'0');
    signal countr:std_logic_vector(2 downto 0);
    signal countf:std_logic_vector(2 downto 0);
    signal levelr:std_logic;
    signal levelf:std_logic;
begin
  process(clk)
	  begin
	       if(clk'event and clk='1')then
			   if(countr=md)then
				   countr<=zero;
				else
			   	countr<=countr+1;
			   end if;
			 end if;
		end process;
		process(clk)
		begin
			  if(clk'event and clk='0')then
				  if (countf=md)then
				      countf<=zero;
				  else
				      countf<=countf+1;
				  end if;
				end if;
		end process;
		process(clk)
		begin
			  if(clk'event and clk='1')then
			     if(countr=zero)then
				     levelr<='1';
				  elsif(countr=ld)then
				      levelr<='0';
				  end if;
			   end if;
		end process;
		process(clk)
		begin
			  if(clk'event and clk='0')then
			     if(countr=zero)then
				      levelr<='1';
			     elsif(countr=ld)then
				       levelr<='0';
				  end if;
			  end if;
		end process;
		clk_div5<=levelr or levelf;
end Behavioral;