demo.tan.qmsg

用硬件VHDL语言实现的串口通信的试验代码

{ "Info" "ITDB_FULL_MIN_TCO_RESULT" "clk tdempty tdempty~reg0 6.796 ns register " "Info: Minimum tco from clock \"clk\" to destination pin \"tdempty\" through register \"tdempty~reg0\" is 6.796 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 2.743 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to source register is 2.743 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_16 51 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_16; Fanout = 51; CLK Node = 'clk'" {  } { { "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "serialout.vhd" "" { Text "E:/download/资料备份/史磊的资料/ic设计/fpga/FPGA开发板DEMO程序/003实验三 串口发送实验/serialout.vhd" 22 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.563 ns) + CELL(0.711 ns) 2.743 ns tdempty~reg0 2 REG LC_X18_Y5_N2 1 " "Info: 2: + IC(0.563 ns) + CELL(0.711 ns) = 2.743 ns; Loc. = LC_X18_Y5_N2; Fanout = 1; REG Node = 'tdempty~reg0'" {  } { { "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "1.274 ns" { clk tdempty~reg0 } "NODE_NAME" } } { "serialout.vhd" "" { Text "E:/download/资料备份/史磊的资料/ic设计/fpga/FPGA开发板DEMO程序/003实验三 串口发送实验/serialout.vhd" 41 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 79.48 % ) " "Info: Total cell delay = 2.180 ns ( 79.48 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.563 ns ( 20.52 % ) " "Info: Total interconnect delay = 0.563 ns ( 20.52 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "2.743 ns" { clk tdempty~reg0 } "NODE_NAME" } } { "d:/altera/61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/61/quartus/bin/Technology_Viewer.qrui" "2.743 ns" { clk clk~out0 tdempty~reg0 } { 0.000ns 0.000ns 0.563ns } { 0.000ns 1.469ns 0.711ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" {  } { { "serialout.vhd" "" { Text "E:/download/资料备份/史磊的资料/ic设计/fpga/FPGA开发板DEMO程序/003实验三 串口发送实验/serialout.vhd" 41 0 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.829 ns + Shortest register pin " "Info: + Shortest register to pin delay is 3.829 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns tdempty~reg0 1 REG LC_X18_Y5_N2 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X18_Y5_N2; Fanout = 1; REG Node = 'tdempty~reg0'" {  } { { "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "" { tdempty~reg0 } "NODE_NAME" } } { "serialout.vhd" "" { Text "E:/download/资料备份/史磊的资料/ic设计/fpga/FPGA开发板DEMO程序/003实验三 串口发送实验/serialout.vhd" 41 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.721 ns) + CELL(2.108 ns) 3.829 ns tdempty 2 PIN PIN_58 0 " "Info: 2: + IC(1.721 ns) + CELL(2.108 ns) = 3.829 ns; Loc. = PIN_58; Fanout = 0; PIN Node = 'tdempty'" {  } { { "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "3.829 ns" { tdempty~reg0 tdempty } "NODE_NAME" } } { "serialout.vhd" "" { Text "E:/download/资料备份/史磊的资料/ic设计/fpga/FPGA开发板DEMO程序/003实验三 串口发送实验/serialout.vhd" 25 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.108 ns ( 55.05 % ) " "Info: Total cell delay = 2.108 ns ( 55.05 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.721 ns ( 44.95 % ) " "Info: Total interconnect delay = 1.721 ns ( 44.95 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "3.829 ns" { tdempty~reg0 tdempty } "NODE_NAME" } } { "d:/altera/61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/61/quartus/bin/Technology_Viewer.qrui" "3.829 ns" { tdempty~reg0 tdempty } { 0.000ns 1.721ns } { 0.000ns 2.108ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "2.743 ns" { clk tdempty~reg0 } "NODE_NAME" } } { "d:/altera/61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/61/quartus/bin/Technology_Viewer.qrui" "2.743 ns" { clk clk~out0 tdempty~reg0 } { 0.000ns 0.000ns 0.563ns } { 0.000ns 1.469ns 0.711ns } "" } } { "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "3.829 ns" { tdempty~reg0 tdempty } "NODE_NAME" } } { "d:/altera/61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/61/quartus/bin/Technology_Viewer.qrui" "3.829 ns" { tdempty~reg0 tdempty } { 0.000ns 1.721ns } { 0.000ns 2.108ns } "" } }  } 0 0 "Minimum tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Classic Timing Analyzer 0 s 1  Quartus II " "Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "104 " "Info: Allocated 104 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0} { "Info" "IQEXE_END_BANNER_TIME" "Mon Jun 25 17:23:02 2007 " "Info: Processing ended: Mon Jun 25 17:23:02 2007" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}