demo.tan.qmsg

用硬件VHDL语言实现的串口通信的试验代码

{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk register xbitcnt\[22\] register xbitcnt\[26\] 160.08 MHz 6.247 ns Internal " "Info: Clock \"clk\" has Internal fmax of 160.08 MHz between source register \"xbitcnt\[22\]\" and destination register \"xbitcnt\[26\]\" (period= 6.247 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.947 ns + Longest register register " "Info: + Longest register to register delay is 5.947 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns xbitcnt\[22\] 1 REG LC_X17_Y6_N6 4 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X17_Y6_N6; Fanout = 4; REG Node = 'xbitcnt\[22\]'" {  } { { "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "" { xbitcnt[22] } "NODE_NAME" } } { "serialout.vhd" "" { Text "E:/download/资料备份/史磊的资料/ic设计/fpga/FPGA开发板DEMO程序/003实验三 串口发送实验/serialout.vhd" 41 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.779 ns) + CELL(0.590 ns) 1.369 ns Equal2~360 2 COMB LC_X18_Y6_N5 1 " "Info: 2: + IC(0.779 ns) + CELL(0.590 ns) = 1.369 ns; Loc. = LC_X18_Y6_N5; Fanout = 1; COMB Node = 'Equal2~360'" {  } { { "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "1.369 ns" { xbitcnt[22] Equal2~360 } "NODE_NAME" } } { "serialout.vhd" "" { Text "E:/download/资料备份/史磊的资料/ic设计/fpga/FPGA开发板DEMO程序/003实验三 串口发送实验/serialout.vhd" 61 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.418 ns) + CELL(0.114 ns) 1.901 ns Equal2~361 3 COMB LC_X18_Y6_N0 1 " "Info: 3: + IC(0.418 ns) + CELL(0.114 ns) = 1.901 ns; Loc. = LC_X18_Y6_N0; Fanout = 1; COMB Node = 'Equal2~361'" {  } { { "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "0.532 ns" { Equal2~360 Equal2~361 } "NODE_NAME" } } { "serialout.vhd" "" { Text "E:/download/资料备份/史磊的资料/ic设计/fpga/FPGA开发板DEMO程序/003实验三 串口发送实验/serialout.vhd" 61 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.269 ns) + CELL(0.292 ns) 3.462 ns Equal2~364 4 COMB LC_X18_Y8_N8 3 " "Info: 4: + IC(1.269 ns) + CELL(0.292 ns) = 3.462 ns; Loc. = LC_X18_Y8_N8; Fanout = 3; COMB Node = 'Equal2~364'" {  } { { "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "1.561 ns" { Equal2~361 Equal2~364 } "NODE_NAME" } } { "serialout.vhd" "" { Text "E:/download/资料备份/史磊的资料/ic设计/fpga/FPGA开发板DEMO程序/003实验三 串口发送实验/serialout.vhd" 61 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.182 ns) + CELL(0.114 ns) 3.758 ns xbitcnt\[12\]~1479 5 COMB LC_X18_Y8_N9 32 " "Info: 5: + IC(0.182 ns) + CELL(0.114 ns) = 3.758 ns; Loc. = LC_X18_Y8_N9; Fanout = 32; COMB Node = 'xbitcnt\[12\]~1479'" {  } { { "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "0.296 ns" { Equal2~364 xbitcnt[12]~1479 } "NODE_NAME" } } { "serialout.vhd" "" { Text "E:/download/资料备份/史磊的资料/ic设计/fpga/FPGA开发板DEMO程序/003实验三 串口发送实验/serialout.vhd" 41 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.322 ns) + CELL(0.867 ns) 5.947 ns xbitcnt\[26\] 6 REG LC_X17_Y5_N0 4 " "Info: 6: + IC(1.322 ns) + CELL(0.867 ns) = 5.947 ns; Loc. = LC_X17_Y5_N0; Fanout = 4; REG Node = 'xbitcnt\[26\]'" {  } { { "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "2.189 ns" { xbitcnt[12]~1479 xbitcnt[26] } "NODE_NAME" } } { "serialout.vhd" "" { Text "E:/download/资料备份/史磊的资料/ic设计/fpga/FPGA开发板DEMO程序/003实验三 串口发送实验/serialout.vhd" 41 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.977 ns ( 33.24 % ) " "Info: Total cell delay = 1.977 ns ( 33.24 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.970 ns ( 66.76 % ) " "Info: Total interconnect delay = 3.970 ns ( 66.76 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "5.947 ns" { xbitcnt[22] Equal2~360 Equal2~361 Equal2~364 xbitcnt[12]~1479 xbitcnt[26] } "NODE_NAME" } } { "d:/altera/61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/61/quartus/bin/Technology_Viewer.qrui" "5.947 ns" { xbitcnt[22] Equal2~360 Equal2~361 Equal2~364 xbitcnt[12]~1479 xbitcnt[26] } { 0.000ns 0.779ns 0.418ns 1.269ns 0.182ns 1.322ns } { 0.000ns 0.590ns 0.114ns 0.292ns 0.114ns 0.867ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "-0.039 ns - Smallest " "Info: - Smallest clock skew is -0.039 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.743 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 2.743 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_16 51 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_16; Fanout = 51; CLK Node = 'clk'" {  } { { "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "serialout.vhd" "" { Text "E:/download/资料备份/史磊的资料/ic设计/fpga/FPGA开发板DEMO程序/003实验三 串口发送实验/serialout.vhd" 22 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.563 ns) + CELL(0.711 ns) 2.743 ns xbitcnt\[26\] 2 REG LC_X17_Y5_N0 4 " "Info: 2: + IC(0.563 ns) + CELL(0.711 ns) = 2.743 ns; Loc. = LC_X17_Y5_N0; Fanout = 4; REG Node = 'xbitcnt\[26\]'" {  } { { "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "1.274 ns" { clk xbitcnt[26] } "NODE_NAME" } } { "serialout.vhd" "" { Text "E:/download/资料备份/史磊的资料/ic设计/fpga/FPGA开发板DEMO程序/003实验三 串口发送实验/serialout.vhd" 41 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 79.48 % ) " "Info: Total cell delay = 2.180 ns ( 79.48 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.563 ns ( 20.52 % ) " "Info: Total interconnect delay = 0.563 ns ( 20.52 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "2.743 ns" { clk xbitcnt[26] } "NODE_NAME" } } { "d:/altera/61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/61/quartus/bin/Technology_Viewer.qrui" "2.743 ns" { clk clk~out0 xbitcnt[26] } { 0.000ns 0.000ns 0.563ns } { 0.000ns 1.469ns 0.711ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 2.782 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 2.782 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_16 51 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_16; Fanout = 51; CLK Node = 'clk'" {  } { { "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "serialout.vhd" "" { Text "E:/download/资料备份/史磊的资料/ic设计/fpga/FPGA开发板DEMO程序/003实验三 串口发送实验/serialout.vhd" 22 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.602 ns) + CELL(0.711 ns) 2.782 ns xbitcnt\[22\] 2 REG LC_X17_Y6_N6 4 " "Info: 2: + IC(0.602 ns) + CELL(0.711 ns) = 2.782 ns; Loc. = LC_X17_Y6_N6; Fanout = 4; REG Node = 'xbitcnt\[22\]'" {  } { { "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "1.313 ns" { clk xbitcnt[22] } "NODE_NAME" } } { "serialout.vhd" "" { Text "E:/download/资料备份/史磊的资料/ic设计/fpga/FPGA开发板DEMO程序/003实验三 串口发送实验/serialout.vhd" 41 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 78.36 % ) " "Info: Total cell delay = 2.180 ns ( 78.36 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.602 ns ( 21.64 % ) " "Info: Total interconnect delay = 0.602 ns ( 21.64 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "2.782 ns" { clk xbitcnt[22] } "NODE_NAME" } } { "d:/altera/61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/61/quartus/bin/Technology_Viewer.qrui" "2.782 ns" { clk clk~out0 xbitcnt[22] } { 0.000ns 0.000ns 0.602ns } { 0.000ns 1.469ns 0.711ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "2.743 ns" { clk xbitcnt[26] } "NODE_NAME" } } { "d:/altera/61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/61/quartus/bin/Technology_Viewer.qrui" "2.743 ns" { clk clk~out0 xbitcnt[26] } { 0.000ns 0.000ns 0.563ns } { 0.000ns 1.469ns 0.711ns } "" } } { "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "2.782 ns" { clk xbitcnt[22] } "NODE_NAME" } } { "d:/altera/61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/61/quartus/bin/Technology_Viewer.qrui" "2.782 ns" { clk clk~out0 xbitcnt[22] } { 0.000ns 0.000ns 0.602ns } { 0.000ns 1.469ns 0.711ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" {  } { { "serialout.vhd" "" { Text "E:/download/资料备份/史磊的资料/ic设计/fpga/FPGA开发板DEMO程序/003实验三 串口发送实验/serialout.vhd" 41 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns + " "Info: + Micro setup delay of destination is 0.037 ns" {  } { { "serialout.vhd" "" { Text "E:/download/资料备份/史磊的资料/ic设计/fpga/FPGA开发板DEMO程序/003实验三 串口发送实验/serialout.vhd" 41 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0}  } { { "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "5.947 ns" { xbitcnt[22] Equal2~360 Equal2~361 Equal2~364 xbitcnt[12]~1479 xbitcnt[26] } "NODE_NAME" } } { "d:/altera/61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/61/quartus/bin/Technology_Viewer.qrui" "5.947 ns" { xbitcnt[22] Equal2~360 Equal2~361 Equal2~364 xbitcnt[12]~1479 xbitcnt[26] } { 0.000ns 0.779ns 0.418ns 1.269ns 0.182ns 1.322ns } { 0.000ns 0.590ns 0.114ns 0.292ns 0.114ns 0.867ns } "" } } { "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "2.743 ns" { clk xbitcnt[26] } "NODE_NAME" } } { "d:/altera/61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/61/quartus/bin/Technology_Viewer.qrui" "2.743 ns" { clk clk~out0 xbitcnt[26] } { 0.000ns 0.000ns 0.563ns } { 0.000ns 1.469ns 0.711ns } "" } } { "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "2.782 ns" { clk xbitcnt[22] } "NODE_NAME" } } { "d:/altera/61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/61/quartus/bin/Technology_Viewer.qrui" "2.782 ns" { clk clk~out0 xbitcnt[22] } { 0.000ns 0.000ns 0.602ns } { 0.000ns 1.469ns 0.711ns } "" } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0}
{ "Info" "ITDB_TSU_RESULT" "qinbuf\[4\] wr clk 7.216 ns register " "Info: tsu for register \"qinbuf\[4\]\" (data pin = \"wr\", clock pin = \"clk\") is 7.216 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "9.961 ns + Longest pin register " "Info: + Longest pin to register delay is 9.961 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.475 ns) 1.475 ns wr 1 PIN PIN_59 3 " "Info: 1: + IC(0.000 ns) + CELL(1.475 ns) = 1.475 ns; Loc. = PIN_59; Fanout = 3; PIN Node = 'wr'" {  } { { "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "" { wr } "NODE_NAME" } } { "serialout.vhd" "" { Text "E:/download/资料备份/史磊的资料/ic设计/fpga/FPGA开发板DEMO程序/003实验三 串口发送实验/serialout.vhd" 23 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(5.509 ns) + CELL(0.442 ns) 7.426 ns Selector1~60 2 COMB LC_X18_Y6_N2 8 " "Info: 2: + IC(5.509 ns) + CELL(0.442 ns) = 7.426 ns; Loc. = LC_X18_Y6_N2; Fanout = 8; COMB Node = 'Selector1~60'" {  } { { "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "5.951 ns" { wr Selector1~60 } "NODE_NAME" } } { "serialout.vhd" "" { Text "E:/download/资料备份/史磊的资料/ic设计/fpga/FPGA开发板DEMO程序/003实验三 串口发送实验/serialout.vhd" 42 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.668 ns) + CELL(0.867 ns) 9.961 ns qinbuf\[4\] 3 REG LC_X16_Y8_N7 1 " "Info: 3: + IC(1.668 ns) + CELL(0.867 ns) = 9.961 ns; Loc. = LC_X16_Y8_N7; Fanout = 1; REG Node = 'qinbuf\[4\]'" {  } { { "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "2.535 ns" { Selector1~60 qinbuf[4] } "NODE_NAME" } } { "serialout.vhd" "" { Text "E:/download/资料备份/史磊的资料/ic设计/fpga/FPGA开发板DEMO程序/003实验三 串口发送实验/serialout.vhd" 41 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.784 ns ( 27.95 % ) " "Info: Total cell delay = 2.784 ns ( 27.95 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "7.177 ns ( 72.05 % ) " "Info: Total interconnect delay = 7.177 ns ( 72.05 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "9.961 ns" { wr Selector1~60 qinbuf[4] } "NODE_NAME" } } { "d:/altera/61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/61/quartus/bin/Technology_Viewer.qrui" "9.961 ns" { wr wr~out0 Selector1~60 qinbuf[4] } { 0.000ns 0.000ns 5.509ns 1.668ns } { 0.000ns 1.475ns 0.442ns 0.867ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns + " "Info: + Micro setup delay of destination is 0.037 ns" {  } { { "serialout.vhd" "" { Text "E:/download/资料备份/史磊的资料/ic设计/fpga/FPGA开发板DEMO程序/003实验三 串口发送实验/serialout.vhd" 41 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.782 ns - Shortest register " "Info: - Shortest clock path from clock \"clk\" to destination register is 2.782 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_16 51 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_16; Fanout = 51; CLK Node = 'clk'" {  } { { "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "serialout.vhd" "" { Text "E:/download/资料备份/史磊的资料/ic设计/fpga/FPGA开发板DEMO程序/003实验三 串口发送实验/serialout.vhd" 22 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.602 ns) + CELL(0.711 ns) 2.782 ns qinbuf\[4\] 2 REG LC_X16_Y8_N7 1 " "Info: 2: + IC(0.602 ns) + CELL(0.711 ns) = 2.782 ns; Loc. = LC_X16_Y8_N7; Fanout = 1; REG Node = 'qinbuf\[4\]'" {  } { { "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "1.313 ns" { clk qinbuf[4] } "NODE_NAME" } } { "serialout.vhd" "" { Text "E:/download/资料备份/史磊的资料/ic设计/fpga/FPGA开发板DEMO程序/003实验三 串口发送实验/serialout.vhd" 41 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 78.36 % ) " "Info: Total cell delay = 2.180 ns ( 78.36 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.602 ns ( 21.64 % ) " "Info: Total interconnect delay = 0.602 ns ( 21.64 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "2.782 ns" { clk qinbuf[4] } "NODE_NAME" } } { "d:/altera/61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/61/quartus/bin/Technology_Viewer.qrui" "2.782 ns" { clk clk~out0 qinbuf[4] } { 0.000ns 0.000ns 0.602ns } { 0.000ns 1.469ns 0.711ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "9.961 ns" { wr Selector1~60 qinbuf[4] } "NODE_NAME" } } { "d:/altera/61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/61/quartus/bin/Technology_Viewer.qrui" "9.961 ns" { wr wr~out0 Selector1~60 qinbuf[4] } { 0.000ns 0.000ns 5.509ns 1.668ns } { 0.000ns 1.475ns 0.442ns 0.867ns } "" } } { "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "2.782 ns" { clk qinbuf[4] } "NODE_NAME" } } { "d:/altera/61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/61/quartus/bin/Technology_Viewer.qrui" "2.782 ns" { clk clk~out0 qinbuf[4] } { 0.000ns 0.000ns 0.602ns } { 0.000ns 1.469ns 0.711ns } "" } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk txd txds 7.216 ns register " "Info: tco from clock \"clk\" to destination pin \"txd\" through register \"txds\" is 7.216 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 2.782 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to source register is 2.782 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_16 51 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_16; Fanout = 51; CLK Node = 'clk'" {  } { { "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "serialout.vhd" "" { Text "E:/download/资料备份/史磊的资料/ic设计/fpga/FPGA开发板DEMO程序/003实验三 串口发送实验/serialout.vhd" 22 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.602 ns) + CELL(0.711 ns) 2.782 ns txds 2 REG LC_X18_Y8_N3 2 " "Info: 2: + IC(0.602 ns) + CELL(0.711 ns) = 2.782 ns; Loc. = LC_X18_Y8_N3; Fanout = 2; REG Node = 'txds'" {  } { { "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "1.313 ns" { clk txds } "NODE_NAME" } } { "serialout.vhd" "" { Text "E:/download/资料备份/史磊的资料/ic设计/fpga/FPGA开发板DEMO程序/003实验三 串口发送实验/serialout.vhd" 41 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 78.36 % ) " "Info: Total cell delay = 2.180 ns ( 78.36 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.602 ns ( 21.64 % ) " "Info: Total interconnect delay = 0.602 ns ( 21.64 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "2.782 ns" { clk txds } "NODE_NAME" } } { "d:/altera/61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/61/quartus/bin/Technology_Viewer.qrui" "2.782 ns" { clk clk~out0 txds } { 0.000ns 0.000ns 0.602ns } { 0.000ns 1.469ns 0.711ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" {  } { { "serialout.vhd" "" { Text "E:/download/资料备份/史磊的资料/ic设计/fpga/FPGA开发板DEMO程序/003实验三 串口发送实验/serialout.vhd" 41 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.210 ns + Longest register pin " "Info: + Longest register to pin delay is 4.210 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns txds 1 REG LC_X18_Y8_N3 2 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X18_Y8_N3; Fanout = 2; REG Node = 'txds'" {  } { { "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "" { txds } "NODE_NAME" } } { "serialout.vhd" "" { Text "E:/download/资料备份/史磊的资料/ic设计/fpga/FPGA开发板DEMO程序/003实验三 串口发送实验/serialout.vhd" 41 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.102 ns) + CELL(2.108 ns) 4.210 ns txd 2 PIN PIN_122 0 " "Info: 2: + IC(2.102 ns) + CELL(2.108 ns) = 4.210 ns; Loc. = PIN_122; Fanout = 0; PIN Node = 'txd'" {  } { { "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "4.210 ns" { txds txd } "NODE_NAME" } } { "serialout.vhd" "" { Text "E:/download/资料备份/史磊的资料/ic设计/fpga/FPGA开发板DEMO程序/003实验三 串口发送实验/serialout.vhd" 26 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.108 ns ( 50.07 % ) " "Info: Total cell delay = 2.108 ns ( 50.07 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.102 ns ( 49.93 % ) " "Info: Total interconnect delay = 2.102 ns ( 49.93 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "4.210 ns" { txds txd } "NODE_NAME" } } { "d:/altera/61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/61/quartus/bin/Technology_Viewer.qrui" "4.210 ns" { txds txd } { 0.000ns 2.102ns } { 0.000ns 2.108ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "2.782 ns" { clk txds } "NODE_NAME" } } { "d:/altera/61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/61/quartus/bin/Technology_Viewer.qrui" "2.782 ns" { clk clk~out0 txds } { 0.000ns 0.000ns 0.602ns } { 0.000ns 1.469ns 0.711ns } "" } } { "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "4.210 ns" { txds txd } "NODE_NAME" } } { "d:/altera/61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/61/quartus/bin/Technology_Viewer.qrui" "4.210 ns" { txds txd } { 0.000ns 2.102ns } { 0.000ns 2.108ns } "" } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0}
{ "Info" "ITDB_TH_RESULT" "qinbuf\[1\] qin\[1\] clk -0.862 ns register " "Info: th for register \"qinbuf\[1\]\" (data pin = \"qin\[1\]\", clock pin = \"clk\") is -0.862 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.782 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to destination register is 2.782 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_16 51 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_16; Fanout = 51; CLK Node = 'clk'" {  } { { "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "serialout.vhd" "" { Text "E:/download/资料备份/史磊的资料/ic设计/fpga/FPGA开发板DEMO程序/003实验三 串口发送实验/serialout.vhd" 22 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.602 ns) + CELL(0.711 ns) 2.782 ns qinbuf\[1\] 2 REG LC_X16_Y8_N3 1 " "Info: 2: + IC(0.602 ns) + CELL(0.711 ns) = 2.782 ns; Loc. = LC_X16_Y8_N3; Fanout = 1; REG Node = 'qinbuf\[1\]'" {  } { { "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "1.313 ns" { clk qinbuf[1] } "NODE_NAME" } } { "serialout.vhd" "" { Text "E:/download/资料备份/史磊的资料/ic设计/fpga/FPGA开发板DEMO程序/003实验三 串口发送实验/serialout.vhd" 41 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 78.36 % ) " "Info: Total cell delay = 2.180 ns ( 78.36 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.602 ns ( 21.64 % ) " "Info: Total interconnect delay = 0.602 ns ( 21.64 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "2.782 ns" { clk qinbuf[1] } "NODE_NAME" } } { "d:/altera/61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/61/quartus/bin/Technology_Viewer.qrui" "2.782 ns" { clk clk~out0 qinbuf[1] } { 0.000ns 0.000ns 0.602ns } { 0.000ns 1.469ns 0.711ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TH_DELAY" "0.015 ns + " "Info: + Micro hold delay of destination is 0.015 ns" {  } { { "serialout.vhd" "" { Text "E:/download/资料备份/史磊的资料/ic设计/fpga/FPGA开发板DEMO程序/003实验三 串口发送实验/serialout.vhd" 41 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.659 ns - Shortest pin register " "Info: - Shortest pin to register delay is 3.659 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns qin\[1\] 1 PIN PIN_17 1 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_17; Fanout = 1; PIN Node = 'qin\[1\]'" {  } { { "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "" { qin[1] } "NODE_NAME" } } { "serialout.vhd" "" { Text "E:/download/资料备份/史磊的资料/ic设计/fpga/FPGA开发板DEMO程序/003实验三 串口发送实验/serialout.vhd" 24 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.075 ns) + CELL(0.115 ns) 3.659 ns qinbuf\[1\] 2 REG LC_X16_Y8_N3 1 " "Info: 2: + IC(2.075 ns) + CELL(0.115 ns) = 3.659 ns; Loc. = LC_X16_Y8_N3; Fanout = 1; REG Node = 'qinbuf\[1\]'" {  } { { "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "2.190 ns" { qin[1] qinbuf[1] } "NODE_NAME" } } { "serialout.vhd" "" { Text "E:/download/资料备份/史磊的资料/ic设计/fpga/FPGA开发板DEMO程序/003实验三 串口发送实验/serialout.vhd" 41 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.584 ns ( 43.29 % ) " "Info: Total cell delay = 1.584 ns ( 43.29 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.075 ns ( 56.71 % ) " "Info: Total interconnect delay = 2.075 ns ( 56.71 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "3.659 ns" { qin[1] qinbuf[1] } "NODE_NAME" } } { "d:/altera/61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/61/quartus/bin/Technology_Viewer.qrui" "3.659 ns" { qin[1] qin[1]~out0 qinbuf[1] } { 0.000ns 0.000ns 2.075ns } { 0.000ns 1.469ns 0.115ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "2.782 ns" { clk qinbuf[1] } "NODE_NAME" } } { "d:/altera/61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/61/quartus/bin/Technology_Viewer.qrui" "2.782 ns" { clk clk~out0 qinbuf[1] } { 0.000ns 0.000ns 0.602ns } { 0.000ns 1.469ns 0.711ns } "" } } { "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "3.659 ns" { qin[1] qinbuf[1] } "NODE_NAME" } } { "d:/altera/61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/61/quartus/bin/Technology_Viewer.qrui" "3.659 ns" { qin[1] qin[1]~out0 qinbuf[1] } { 0.000ns 0.000ns 2.075ns } { 0.000ns 1.469ns 0.115ns } "" } }  } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}