demo.map.rpt

用硬件VHDL语言实现的串口通信的试验代码

; Analysis & Synthesis Resource Usage Summary         ;
+---------------------------------------------+-------+
; Resource                                    ; Usage ;
+---------------------------------------------+-------+
; Total logic elements                        ; 77    ;
;     -- Combinational with no register       ; 26    ;
;     -- Register only                        ; 8     ;
;     -- Combinational with a register        ; 43    ;
;                                             ;       ;
; Logic element usage by number of LUT inputs ;       ;
;     -- 4 input functions                    ; 27    ;
;     -- 3 input functions                    ; 3     ;
;     -- 2 input functions                    ; 37    ;
;     -- 1 input functions                    ; 2     ;
;     -- 0 input functions                    ; 0     ;
;                                             ;       ;
; Logic elements by mode                      ;       ;
;     -- normal mode                          ; 46    ;
;     -- arithmetic mode                      ; 31    ;
;     -- qfbk mode                            ; 0     ;
;     -- register cascade mode                ; 0     ;
;     -- synchronous clear/load mode          ; 32    ;
;     -- asynchronous clear/load mode         ; 0     ;
;                                             ;       ;
; Total registers                             ; 51    ;
; Total logic cells in carry chains           ; 32    ;
; I/O pins                                    ; 12    ;
; Maximum fan-out node                        ; clk   ;
; Maximum fan-out                             ; 51    ;
; Total fan-out                               ; 330   ;
; Average fan-out                             ; 3.71  ;
+---------------------------------------------+-------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity                                                                                                                                                    ;
+----------------------------+-------------+--------------+-------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------+
; Compilation Hierarchy Node ; Logic Cells ; LC Registers ; Memory Bits ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Packed LCs ; Full Hierarchy Name ;
+----------------------------+-------------+--------------+-------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------+
; |serialout                 ; 77 (77)     ; 51           ; 0           ; 12   ; 0            ; 26 (26)      ; 8 (8)             ; 43 (43)          ; 32 (32)         ; 0 (0)      ; |serialout          ;
+----------------------------+-------------+--------------+-------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.


Encoding Type:  One-Hot
+--------------------------------------------------------------------------------------------+
; State Machine - |serialout|state                                                           ;
+---------------+--------------+---------------+--------------+---------------+--------------+
; Name          ; state.x_stop ; state.x_shift ; state.x_wait ; state.x_start ; state.x_idle ;
+---------------+--------------+---------------+--------------+---------------+--------------+
; state.x_idle  ; 0            ; 0             ; 0            ; 0             ; 0            ;
; state.x_start ; 0            ; 0             ; 0            ; 1             ; 1            ;
; state.x_wait  ; 0            ; 0             ; 1            ; 0             ; 1            ;
; state.x_shift ; 0            ; 1             ; 0            ; 0             ; 1            ;
; state.x_stop  ; 1            ; 0             ; 0            ; 0             ; 1            ;
+---------------+--------------+---------------+--------------+---------------+--------------+


+------------------------------------------------------+
; General Register Statistics                          ;
+----------------------------------------------+-------+
; Statistic                                    ; Value ;
+----------------------------------------------+-------+
; Total registers                              ; 51    ;
; Number of registers using Synchronous Clear  ; 32    ;
; Number of registers using Synchronous Load   ; 0     ;
; Number of registers using Asynchronous Clear ; 0     ;
; Number of registers using Asynchronous Load  ; 0     ;
; Number of registers using Clock Enable       ; 44    ;
; Number of registers using Preset             ; 0     ;
+----------------------------------------------+-------+


+------------------------------------------------------------------------------------------------------------------------------------------+
; Multiplexer Restructuring Statistics (Restructuring Performed)                                                                           ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+
; Multiplexer Inputs ; Bus Width ; Baseline Area ; Area if Restructured ; Saving if Restructured ; Registered ; Example Multiplexer Output ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+
; 5:1                ; 32 bits   ; 96 LEs        ; 32 LEs               ; 64 LEs                 ; Yes        ; |serialout|xbitcnt[12]     ;
; 5:1                ; 4 bits    ; 12 LEs        ; 4 LEs                ; 8 LEs                  ; Yes        ; |serialout|xcnt[0]         ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 6.1 Build 201 11/27/2006 SJ Full Version
    Info: Processing started: Mon Jun 25 17:22:39 2007
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off demo -c demo
Info: Found 1 design units, including 1 entities, in source file demo.bdf
    Info: Found entity 1: demo
Info: Found 2 design units, including 1 entities, in source file fen1250.vhd
    Info: Found design unit 1: fen1250-behave
    Info: Found entity 1: fen1250
Info: Found 2 design units, including 1 entities, in source file sentword.vhd
    Info: Found design unit 1: sentword-behave
    Info: Found entity 1: sentword
Info: Found 2 design units, including 1 entities, in source file serialout.vhd
    Info: Found design unit 1: serialout-behave
    Info: Found entity 1: serialout
Info: Elaborating entity "serialout" for the top level hierarchy
Info: State machine "|serialout|state" contains 5 states
Info: Selected Auto state machine encoding method for state machine "|serialout|state"
Info: Encoding result for state machine "|serialout|state"
    Info: Completed encoding using 5 state bits
        Info: Encoded state bit "state.x_stop"
        Info: Encoded state bit "state.x_shift"
        Info: Encoded state bit "state.x_wait"
        Info: Encoded state bit "state.x_start"
        Info: Encoded state bit "state.x_idle"
    Info: State "|serialout|state.x_idle" uses code string "00000"
    Info: State "|serialout|state.x_start" uses code string "00011"
    Info: State "|serialout|state.x_wait" uses code string "00101"
    Info: State "|serialout|state.x_shift" uses code string "01001"
    Info: State "|serialout|state.x_stop" uses code string "10001"
Info: Implemented 89 device resources after synthesis - the final resource count might be different
    Info: Implemented 10 input pins
    Info: Implemented 2 output pins
    Info: Implemented 77 logic cells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 0 warnings
    Info: Allocated 145 megabytes of memory during processing
    Info: Processing ended: Mon Jun 25 17:22:43 2007
    Info: Elapsed time: 00:00:04