demo.fit.smsg

用硬件VHDL语言实现的串口通信的试验代码

Info: *******************************************************************
Info: Running Quartus II Fitter
    Info: Version 6.1 Build 201 11/27/2006 SJ Full Version
    Info: Processing started: Mon Jun 25 17:22:45 2007
Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off demo -c demo
Info: Selected device EP1C3T144C8 for design "demo"
Info: Fitter is performing a Standard Fit compilation using maximum Fitter effort to optimize design performance
Info: Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices
    Info: Device EP1C6T144C8 is compatible
Info: Fitter converted 2 user pins into dedicated programming pins
    Info: Pin ~nCSO~ is reserved at location 12
    Info: Pin ~ASDO~ is reserved at location 25
Warning: No exact pin location assignment(s) for 11 pins of 12 total pins
    Info: Pin tdempty not assigned to an exact location on the device
    Info: Pin txd not assigned to an exact location on the device
    Info: Pin wr not assigned to an exact location on the device
    Info: Pin qin[5] not assigned to an exact location on the device
    Info: Pin qin[6] not assigned to an exact location on the device
    Info: Pin qin[4] not assigned to an exact location on the device
    Info: Pin qin[7] not assigned to an exact location on the device
    Info: Pin qin[2] not assigned to an exact location on the device
    Info: Pin qin[1] not assigned to an exact location on the device
    Info: Pin qin[0] not assigned to an exact location on the device
    Info: Pin qin[3] not assigned to an exact location on the device
Info: Fitter is using the Classic Timing Analyzer
Info: Timing requirements not specified -- optimizing circuit to achieve the following default global requirements
    Info: Assuming a global fmax requirement of 1000 MHz
    Info: Not setting a global tsu requirement
    Info: Not setting a global tco requirement
    Info: Not setting a global tpd requirement
Info: Completed User Assigned Global Signals Promotion Operation
Info: DQS I/O pins require 0 global routing resources
Info: Automatically promoted signal "clk" to use Global clock in PIN 16
Info: Completed Auto Global Promotion Operation
Info: Starting register packing
Info: Fitter is using Normal packing mode for logic elements with Auto setting for Auto Packed Registers logic option
Info: Finished moving registers into I/O cells, LUTs, and RAM blocks
Info: Finished register packing: elapsed time is 00:00:00
Info: Statistics of I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement
    Info: Number of I/O pins in group: 11 (unused VREF, 3.30 VCCIO, 9 input, 2 output, 0 bidirectional)
        Info: I/O standards used: 3.3-V LVTTL.
Info: I/O bank details before I/O pin placement
    Info: Statistics of I/O banks
        Info: I/O bank number 1 does not use VREF pins and has unused VCCIO pins. 3 total pin(s) used --  19 pins available
        Info: I/O bank number 2 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  28 pins available
        Info: I/O bank number 3 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  26 pins available
        Info: I/O bank number 4 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  28 pins available
Warning: Ignored locations or region assignments to the following nodes
    Warning: Node "rs232out" is assigned to location or region, but does not exist in design
Info: Fitter placement preparation operations beginning
Info: Fitter placement preparation operations ending: elapsed time is 00:00:00
Info: Fitter placement operations beginning
Info: Fitter placement was successful
Info: Fitter placement operations ending: elapsed time is 00:00:01
Info: Estimated most critical path is register to register delay of 5.659 ns
    Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LAB_X17_Y6; Fanout = 4; REG Node = 'xbitcnt[23]'
    Info: 2: + IC(0.855 ns) + CELL(0.114 ns) = 0.969 ns; Loc. = LAB_X18_Y6; Fanout = 1; COMB Node = 'Equal2~360'
    Info: 3: + IC(0.540 ns) + CELL(0.114 ns) = 1.623 ns; Loc. = LAB_X18_Y6; Fanout = 1; COMB Node = 'Equal2~361'
    Info: 4: + IC(0.922 ns) + CELL(0.442 ns) = 2.987 ns; Loc. = LAB_X18_Y8; Fanout = 3; COMB Node = 'Equal2~364'
    Info: 5: + IC(0.212 ns) + CELL(0.442 ns) = 3.641 ns; Loc. = LAB_X18_Y8; Fanout = 32; COMB Node = 'xbitcnt[12]~1479'
    Info: 6: + IC(1.151 ns) + CELL(0.867 ns) = 5.659 ns; Loc. = LAB_X17_Y5; Fanout = 4; REG Node = 'xbitcnt[26]'
    Info: Total cell delay = 1.979 ns ( 34.97 % )
    Info: Total interconnect delay = 3.680 ns ( 65.03 % )
Info: Fitter routing operations beginning
Info: Average interconnect usage is 0% of the available device resources. Peak interconnect usage is 0%
    Info: The peak interconnect region extends from location X14_Y0 to location X27_Y14
Info: Fitter routing operations ending: elapsed time is 00:00:00
Info: Completed Fixed Delay Chain Operation
Info: Started post-fitting delay annotation
Info: Delay annotation completed successfully
Info: Completed Auto Delay Chain Operation
Warning: The Reserve All Unused Pins setting has not been specified, and will default to 'As output driving ground'.
Info: Quartus II Fitter was successful. 0 errors, 4 warnings
    Info: Allocated 171 megabytes of memory during processing
    Info: Processing ended: Mon Jun 25 17:22:52 2007
    Info: Elapsed time: 00:00:07