demo.tan.rpt

用硬件VHDL语言实现的串口通信的试验代码

; N/A           ; None        ; -4.426 ns ; qin[0] ; qinbuf[0]     ; clk      ;
; N/A           ; None        ; -4.474 ns ; qin[7] ; qinbuf[7]     ; clk      ;
; N/A           ; None        ; -4.794 ns ; wr     ; state.x_start ; clk      ;
; N/A           ; None        ; -4.795 ns ; wr     ; state.x_idle  ; clk      ;
; N/A           ; None        ; -7.164 ns ; wr     ; qinbuf[4]     ; clk      ;
; N/A           ; None        ; -7.164 ns ; wr     ; qinbuf[6]     ; clk      ;
; N/A           ; None        ; -7.164 ns ; wr     ; qinbuf[7]     ; clk      ;
; N/A           ; None        ; -7.164 ns ; wr     ; qinbuf[5]     ; clk      ;
; N/A           ; None        ; -7.164 ns ; wr     ; qinbuf[0]     ; clk      ;
; N/A           ; None        ; -7.164 ns ; wr     ; qinbuf[1]     ; clk      ;
; N/A           ; None        ; -7.164 ns ; wr     ; qinbuf[3]     ; clk      ;
; N/A           ; None        ; -7.164 ns ; wr     ; qinbuf[2]     ; clk      ;
+---------------+-------------+-----------+--------+---------------+----------+


+-----------------------------------------------------------------------------------------+
; Minimum tco                                                                             ;
+---------------+------------------+----------------+--------------+---------+------------+
; Minimum Slack ; Required Min tco ; Actual Min tco ; From         ; To      ; From Clock ;
+---------------+------------------+----------------+--------------+---------+------------+
; N/A           ; None             ; 6.796 ns       ; tdempty~reg0 ; tdempty ; clk        ;
; N/A           ; None             ; 7.216 ns       ; txds         ; txd     ; clk        ;
+---------------+------------------+----------------+--------------+---------+------------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Classic Timing Analyzer
    Info: Version 6.1 Build 201 11/27/2006 SJ Full Version
    Info: Processing started: Mon Jun 25 17:23:01 2007
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off demo -c demo --timing_analysis_only
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "clk" is an undefined clock
Info: Clock "clk" has Internal fmax of 160.08 MHz between source register "xbitcnt[22]" and destination register "xbitcnt[26]" (period= 6.247 ns)
    Info: + Longest register to register delay is 5.947 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X17_Y6_N6; Fanout = 4; REG Node = 'xbitcnt[22]'
        Info: 2: + IC(0.779 ns) + CELL(0.590 ns) = 1.369 ns; Loc. = LC_X18_Y6_N5; Fanout = 1; COMB Node = 'Equal2~360'
        Info: 3: + IC(0.418 ns) + CELL(0.114 ns) = 1.901 ns; Loc. = LC_X18_Y6_N0; Fanout = 1; COMB Node = 'Equal2~361'
        Info: 4: + IC(1.269 ns) + CELL(0.292 ns) = 3.462 ns; Loc. = LC_X18_Y8_N8; Fanout = 3; COMB Node = 'Equal2~364'
        Info: 5: + IC(0.182 ns) + CELL(0.114 ns) = 3.758 ns; Loc. = LC_X18_Y8_N9; Fanout = 32; COMB Node = 'xbitcnt[12]~1479'
        Info: 6: + IC(1.322 ns) + CELL(0.867 ns) = 5.947 ns; Loc. = LC_X17_Y5_N0; Fanout = 4; REG Node = 'xbitcnt[26]'
        Info: Total cell delay = 1.977 ns ( 33.24 % )
        Info: Total interconnect delay = 3.970 ns ( 66.76 % )
    Info: - Smallest clock skew is -0.039 ns
        Info: + Shortest clock path from clock "clk" to destination register is 2.743 ns
            Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_16; Fanout = 51; CLK Node = 'clk'
            Info: 2: + IC(0.563 ns) + CELL(0.711 ns) = 2.743 ns; Loc. = LC_X17_Y5_N0; Fanout = 4; REG Node = 'xbitcnt[26]'
            Info: Total cell delay = 2.180 ns ( 79.48 % )
            Info: Total interconnect delay = 0.563 ns ( 20.52 % )
        Info: - Longest clock path from clock "clk" to source register is 2.782 ns
            Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_16; Fanout = 51; CLK Node = 'clk'
            Info: 2: + IC(0.602 ns) + CELL(0.711 ns) = 2.782 ns; Loc. = LC_X17_Y6_N6; Fanout = 4; REG Node = 'xbitcnt[22]'
            Info: Total cell delay = 2.180 ns ( 78.36 % )
            Info: Total interconnect delay = 0.602 ns ( 21.64 % )
    Info: + Micro clock to output delay of source is 0.224 ns
    Info: + Micro setup delay of destination is 0.037 ns
Info: tsu for register "qinbuf[4]" (data pin = "wr", clock pin = "clk") is 7.216 ns
    Info: + Longest pin to register delay is 9.961 ns
        Info: 1: + IC(0.000 ns) + CELL(1.475 ns) = 1.475 ns; Loc. = PIN_59; Fanout = 3; PIN Node = 'wr'
        Info: 2: + IC(5.509 ns) + CELL(0.442 ns) = 7.426 ns; Loc. = LC_X18_Y6_N2; Fanout = 8; COMB Node = 'Selector1~60'
        Info: 3: + IC(1.668 ns) + CELL(0.867 ns) = 9.961 ns; Loc. = LC_X16_Y8_N7; Fanout = 1; REG Node = 'qinbuf[4]'
        Info: Total cell delay = 2.784 ns ( 27.95 % )
        Info: Total interconnect delay = 7.177 ns ( 72.05 % )
    Info: + Micro setup delay of destination is 0.037 ns
    Info: - Shortest clock path from clock "clk" to destination register is 2.782 ns
        Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_16; Fanout = 51; CLK Node = 'clk'
        Info: 2: + IC(0.602 ns) + CELL(0.711 ns) = 2.782 ns; Loc. = LC_X16_Y8_N7; Fanout = 1; REG Node = 'qinbuf[4]'
        Info: Total cell delay = 2.180 ns ( 78.36 % )
        Info: Total interconnect delay = 0.602 ns ( 21.64 % )
Info: tco from clock "clk" to destination pin "txd" through register "txds" is 7.216 ns
    Info: + Longest clock path from clock "clk" to source register is 2.782 ns
        Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_16; Fanout = 51; CLK Node = 'clk'
        Info: 2: + IC(0.602 ns) + CELL(0.711 ns) = 2.782 ns; Loc. = LC_X18_Y8_N3; Fanout = 2; REG Node = 'txds'
        Info: Total cell delay = 2.180 ns ( 78.36 % )
        Info: Total interconnect delay = 0.602 ns ( 21.64 % )
    Info: + Micro clock to output delay of source is 0.224 ns
    Info: + Longest register to pin delay is 4.210 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X18_Y8_N3; Fanout = 2; REG Node = 'txds'
        Info: 2: + IC(2.102 ns) + CELL(2.108 ns) = 4.210 ns; Loc. = PIN_122; Fanout = 0; PIN Node = 'txd'
        Info: Total cell delay = 2.108 ns ( 50.07 % )
        Info: Total interconnect delay = 2.102 ns ( 49.93 % )
Info: th for register "qinbuf[1]" (data pin = "qin[1]", clock pin = "clk") is -0.862 ns
    Info: + Longe