fifo_cntl.map.smsg

来自「Verilog HDL 编写的CY7C68013 SLAVE FIFO接口程序」· SMSG 代码 · 共 3 行

Warning (10268): Verilog HDL information at fifo_cntl.v(85): always construct contains both blocking and non-blocking assignments
Info (10281): Verilog HDL Declaration information at fifo_cntl.v(32): object "NUM" differs only in case from object "num" in the same scope