fifo_cntl.fit.summary

来自「Verilog HDL 编写的CY7C68013 SLAVE FIFO接口程序」· SUMMARY 代码 · 共 12 行

Fitter Status : Successful - Sat Jul 26 11:54:08 2008
Quartus II Version : 7.2 Build 151 09/26/2007 SJ Full Version
Revision Name : fifo_cntl
Top-level Entity Name : fifo_cntl
Family : MAX II
Device : EPM1270T144C5
Timing Models : Final
Total logic elements : 61 / 1,270 ( 5 % )
Total pins : 30 / 116 ( 26 % )
Total virtual pins : 0
UFM blocks : 0 / 1 ( 0 % )