fifo_cntl.fit.rpt

Verilog HDL 编写的CY7C68013 SLAVE FIFO接口程序

+------------------------------------------------------------------+
; LAB-wide Signals                                                 ;
+------------------------------------+-----------------------------+
; LAB-wide Signals  (Average = 2.38) ; Number of LABs  (Total = 8) ;
+------------------------------------+-----------------------------+
; 1 Async. clear                     ; 6                           ;
; 1 Clock                            ; 8                           ;
; 1 Clock enable                     ; 5                           ;
+------------------------------------+-----------------------------+


+---------------------------------------------------------------------------+
; LAB Signals Sourced                                                       ;
+---------------------------------------------+-----------------------------+
; Number of Signals Sourced  (Average = 8.00) ; Number of LABs  (Total = 8) ;
+---------------------------------------------+-----------------------------+
; 0                                           ; 0                           ;
; 1                                           ; 1                           ;
; 2                                           ; 0                           ;
; 3                                           ; 0                           ;
; 4                                           ; 1                           ;
; 5                                           ; 0                           ;
; 6                                           ; 0                           ;
; 7                                           ; 0                           ;
; 8                                           ; 1                           ;
; 9                                           ; 1                           ;
; 10                                          ; 2                           ;
; 11                                          ; 2                           ;
+---------------------------------------------+-----------------------------+


+-------------------------------------------------------------------------------+
; LAB Signals Sourced Out                                                       ;
+-------------------------------------------------+-----------------------------+
; Number of Signals Sourced Out  (Average = 5.63) ; Number of LABs  (Total = 8) ;
+-------------------------------------------------+-----------------------------+
; 0                                               ; 0                           ;
; 1                                               ; 1                           ;
; 2                                               ; 1                           ;
; 3                                               ; 0                           ;
; 4                                               ; 1                           ;
; 5                                               ; 0                           ;
; 6                                               ; 1                           ;
; 7                                               ; 2                           ;
; 8                                               ; 1                           ;
; 9                                               ; 0                           ;
; 10                                              ; 1                           ;
+-------------------------------------------------+-----------------------------+


+---------------------------------------------------------------------------+
; LAB Distinct Inputs                                                       ;
+---------------------------------------------+-----------------------------+
; Number of Distinct Inputs  (Average = 7.13) ; Number of LABs  (Total = 8) ;
+---------------------------------------------+-----------------------------+
; 0                                           ; 0                           ;
; 1                                           ; 1                           ;
; 2                                           ; 0                           ;
; 3                                           ; 1                           ;
; 4                                           ; 1                           ;
; 5                                           ; 0                           ;
; 6                                           ; 0                           ;
; 7                                           ; 0                           ;
; 8                                           ; 2                           ;
; 9                                           ; 0                           ;
; 10                                          ; 1                           ;
; 11                                          ; 1                           ;
; 12                                          ; 1                           ;
+---------------------------------------------+-----------------------------+


+--------------------------------------------------------------------+
; Fitter Device Options                                              ;
+----------------------------------------------+---------------------+
; Option                                       ; Setting             ;
+----------------------------------------------+---------------------+
; Enable user-supplied start-up clock (CLKUSR) ; Off                 ;
; Enable device-wide reset (DEV_CLRn)          ; Off                 ;
; Enable device-wide output enable (DEV_OE)    ; Off                 ;
; Enable INIT_DONE output                      ; Off                 ;
; Configuration scheme                         ; Passive Serial      ;
; Reserve all unused pins                      ; As input tri-stated ;
; Base pin-out file on sameframe device        ; Off                 ;
+----------------------------------------------+---------------------+


+-----------------+
; Fitter Messages ;
+-----------------+
Info: *******************************************************************
Info: Running Quartus II Fitter
    Info: Version 7.2 Build 151 09/26/2007 SJ Full Version
    Info: Processing started: Sat Jul 26 11:54:01 2008
Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off fifo_cntl -c fifo_cntl
Info: Selected device EPM1270T144C5 for design "fifo_cntl"
Warning: The high junction temperature operating condition is not set. Assuming a default value of '85'.
Warning: The low junction temperature operating condition is not set. Assuming a default value of '0'.
Info: Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time
Info: Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices
    Info: Device EPM570T144C5 is compatible
    Info: Device EPM570T144I5 is compatible
    Info: Device EPM1270T144I5 is compatible
Info: Fitter is using the Classic Timing Analyzer
Info: Timing requirements not specified -- optimizing circuit to achieve the following default global requirements
    Info: Assuming a global fmax requirement of 1000 MHz
    Info: Assuming a global tsu requirement of 2.0 ns
    Info: Assuming a global tco requirement of 1.0 ns
    Info: Assuming a global tpd requirement of 1.0 ns
Info: Completed User Assigned Global Signals Promotion Operation
Info: Automatically promoted signal "clk" to use Global clock in PIN 20
Info: Automatically promoted some destinations of signal "clk_25M" to use Global clock
    Info: Destination "ifclk" may be non-global or may not use global clock
    Info: Destination "clk_25M" may be non-global or may not use global clock
Info: Automatically promoted some destinations of signal "btn[0]" to use Global clock
    Info: Destination "channel[0]~416" may be non-global or may not use global clock
Info: Pin "btn[0]" drives global clock, but is not placed in a dedicated clock pin position
Info: Completed Auto Global Promotion Operation
Info: Starting register packing
Info: Fitter is using Normal packing mode for logic elements with Auto setting for Auto Packed Registers logic option
Info: Started processing fast register assignments
Info: Finished processing fast register assignments
Info: Finished register packing: elapsed time is 00:00:00
Info: Fitter placement preparation operations beginning
Info: Fitter placement preparation operations ending: elapsed time is 00:00:00
Info: Fitter placement operations beginning
Info: Fitter placement was successful
Info: Fitter placement operations ending: elapsed time is 00:00:00
Info: Estimated most critical path is register to pin delay of 5.277 ns
    Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LAB_X7_Y10; Fanout = 1; REG Node = 'o_data[9]~reg0'
    Info: 2: + IC(2.955 ns) + CELL(2.322 ns) = 5.277 ns; Loc. = PIN_144; Fanout = 0; PIN Node = 'o_data[9]'
    Info: Total cell delay = 2.322 ns ( 44.00 % )
    Info: Total interconnect delay = 2.955 ns ( 56.00 % )
Info: Fitter routing operations beginning
Info: Average interconnect usage is 2% of the available device resources
    Info: Peak interconnect usage is 2% of the available device resources in the region that extends from location X0_Y0 to location X8_Y11
Info: Fitter routing operations ending: elapsed time is 00:00:00
Info: The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce com