📄 fifo_cntl.vwf

📁 Verilog HDL 编写的CY7C68013 SLAVE FIFO接口程序
💻 VWF
📖 第 1 页 / 共 5 页
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			LEVEL 0 FOR 320.0;
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		}
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TRANSITION_LIST("o_data[6]")
{
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			{
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			LEVEL 1 FOR 320.0;
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		{
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			{
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		LEVEL 1 FOR 320.0;
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	}
}

TRANSITION_LIST("o_data[5]")
{
	NODE
	{
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		LEVEL 1 FOR 1444.754;
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		{
			REPEAT = 2;
			LEVEL 0 FOR 320.0;
			LEVEL 1 FOR 320.0;
			LEVEL 0 FOR 320.0;
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		NODE
		{
			REPEAT = 3;
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		{
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		{
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		NODE
		{
			REPEAT = 3;
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			LEVEL 0 FOR 320.0;
			LEVEL 1 FOR 320.0;
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		NODE
		{
			REPEAT = 2;
			LEVEL 0 FOR 320.0;
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		}
💿 文件大小 650 K
👤 上传用户 karon9999
📂 所属分类 VHDL/FPGA/Verilog
🏷️ 相关标签

#Verilog #C68013 #68013 #SLAVE
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