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📄 fifo_cntl.vwf

📁 Verilog HDL 编写的CY7C68013 SLAVE FIFO接口程序
💻 VWF
📖 第 1 页 / 共 5 页
字号:
🔍
12345 
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		LEVEL 0 FOR 4800.0;
		LEVEL 1 FOR 320.0;
		LEVEL 0 FOR 960.0;
		LEVEL 1 FOR 320.0;
		LEVEL 0 FOR 320.0;
		LEVEL 1 FOR 320.0;
		LEVEL 0 FOR 960.0;
		LEVEL 1 FOR 320.0;
		LEVEL 0 FOR 4800.0;
		LEVEL 1 FOR 320.0;
		LEVEL 0 FOR 320.0;
		LEVEL 1 FOR 320.0;
		LEVEL 0 FOR 960.0;
		LEVEL 1 FOR 320.0;
		LEVEL 0 FOR 320.0;
		LEVEL 1 FOR 320.0;
		LEVEL 0 FOR 4800.0;
		LEVEL 1 FOR 320.0;
		LEVEL 0 FOR 960.0;
		LEVEL 1 FOR 320.0;
		LEVEL 0 FOR 320.0;
		LEVEL 1 FOR 320.0;
		LEVEL 0 FOR 960.0;
		LEVEL 1 FOR 320.0;
		LEVEL 0 FOR 4800.0;
		LEVEL 1 FOR 320.0;
		LEVEL 0 FOR 320.0;
		LEVEL 1 FOR 320.0;
		LEVEL 0 FOR 960.0;
		LEVEL 1 FOR 320.0;
		LEVEL 0 FOR 320.0;
		LEVEL 1 FOR 320.0;
		LEVEL 0 FOR 4800.0;
		LEVEL 1 FOR 320.0;
		LEVEL 0 FOR 960.0;
		LEVEL 1 FOR 320.0;
		LEVEL 0 FOR 320.0;
		LEVEL 1 FOR 320.0;
		LEVEL 0 FOR 960.0;
		LEVEL 1 FOR 320.0;
		LEVEL 0 FOR 4800.0;
		LEVEL 1 FOR 320.0;
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