yima.vhd

VHDL语言实现时钟程序

library ieee;
use ieee.std_logic_1164.all;
entity yima is 
port(qin:in std_logic_vector(3 downto 0);
qout:out std_logic_vector(6 downto 0));
end entity yima;
architecture behave of yima is 
begin
qout<="1111110"when qin="0000"else
"0110000"when qin="0001"else
"1101101"when qin="0010"else
"1111001"when qin="0011"else
"0110011"when qin="0100"else
"1011011"when qin= "0101"else
"0011111"when qin="0110"else
"1110000"when qin= "0111"else
"1111111"when qin= "1000"else
"1110011" when qin="1001";

end behave;