adcint.rpt

ADC0809采样控制电路的实现ADC0809是CMOS的8位A/D转换器


Device-Specific Information:                   d:\vhdl\work6 adcint\adcint.rpt
adcint

** LOGIC CELL INTERCONNECTIONS **

Logic Array Block 'B':

                                       Logic cells placed in LAB 'B'
        +----------------------------- LC22 ADDA
        | +--------------------------- LC30 ALE
        | | +------------------------- LC17 LOCK0
        | | | +----------------------- LC31 OE
        | | | | +--------------------- LC28 Q0
        | | | | | +------------------- LC27 Q1
        | | | | | | +----------------- LC26 Q2
        | | | | | | | +--------------- LC21 Q3
        | | | | | | | | +------------- LC20 Q4
        | | | | | | | | | +----------- LC19 Q5
        | | | | | | | | | | +--------- LC18 Q6
        | | | | | | | | | | | +------- LC23 Q7
        | | | | | | | | | | | | +----- LC24 START
        | | | | | | | | | | | | | +--- LC25 current_state1
        | | | | | | | | | | | | | | +- LC29 current_state0
        | | | | | | | | | | | | | | | 
        | | | | | | | | | | | | | | |   Other LABs fed by signals
        | | | | | | | | | | | | | | |   that feed LAB 'B'
LC      | | | | | | | | | | | | | | | | A B |     Logic cells that feed LAB 'B':
LC17 -> - * * * * * * * * * * * * * * | - * | <-- LOCK0
LC25 -> - * * * - - - - - - - - * * * | - * | <-- current_state1
LC29 -> - * * * - - - - - - - - * * * | - * | <-- current_state0

Pin
43   -> - - - - - - - - - - - - - - - | - - | <-- CLK
13   -> - - - - * - - - - - - - - - - | - * | <-- D0
12   -> - - - - - * - - - - - - - - - | - * | <-- D1
11   -> - - - - - - * - - - - - - - - | - * | <-- D2
9    -> - - - - - - - * - - - - - - - | - * | <-- D3
4    -> - - - - - - - - * - - - - - - | - * | <-- D4
8    -> - - - - - - - - - * - - - - - | - * | <-- D5
7    -> - - - - - - - - - - * - - - - | - * | <-- D6
6    -> - - - - - - - - - - - * - - - | - * | <-- D7
5    -> - - - - - - - - - - - - - - * | - * | <-- EOC


* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).


Device-Specific Information:                   d:\vhdl\work6 adcint\adcint.rpt
adcint

** EQUATIONS **

CLK      : INPUT;
D0       : INPUT;
D1       : INPUT;
D2       : INPUT;
D3       : INPUT;
D4       : INPUT;
D5       : INPUT;
D6       : INPUT;
D7       : INPUT;
EOC      : INPUT;

-- Node name is 'ADDA' 
-- Equation name is 'ADDA', location is LC022, type is output.
 ADDA    = LCELL( GND $  VCC);

-- Node name is 'ALE' 
-- Equation name is 'ALE', location is LC030, type is output.
 ALE     = LCELL( _EQ001 $  GND);
  _EQ001 =  current_state0 & !current_state1 & !LOCK0;

-- Node name is ':26' = 'current_state0' 
-- Equation name is 'current_state0', location is LC029, type is buried.
current_state0 = DFFE( _EQ002 $ !LOCK0, GLOBAL( CLK),  VCC,  VCC,  VCC);
  _EQ002 =  current_state1 & !EOC & !LOCK0
         #  current_state0 & !LOCK0;

-- Node name is ':25' = 'current_state1' 
-- Equation name is 'current_state1', location is LC025, type is buried.
current_state1 = DFFE( _EQ003 $ !LOCK0, GLOBAL( CLK),  VCC,  VCC,  VCC);
  _EQ003 =  current_state0 &  current_state1 & !LOCK0
         # !current_state0 & !current_state1 & !LOCK0;

-- Node name is 'LOCK0' = 'current_state2' 
-- Equation name is 'LOCK0', location is LC017, type is output.
 LOCK0   = DFFE( _EQ004 $  GND, GLOBAL( CLK),  VCC,  VCC,  VCC);
  _EQ004 =  current_state0 &  current_state1 & !LOCK0;

-- Node name is 'OE' 
-- Equation name is 'OE', location is LC031, type is output.
 OE      = LCELL( _EQ005 $  LOCK0);
  _EQ005 =  current_state0 &  current_state1 & !LOCK0;

-- Node name is 'Q0' = 'REGL0' 
-- Equation name is 'Q0', location is LC028, type is output.
 Q0      = DFFE( D0 $  GND,  LOCK0,  VCC,  VCC,  VCC);

-- Node name is 'Q1' = 'REGL1' 
-- Equation name is 'Q1', location is LC027, type is output.
 Q1      = DFFE( D1 $  GND,  LOCK0,  VCC,  VCC,  VCC);

-- Node name is 'Q2' = 'REGL2' 
-- Equation name is 'Q2', location is LC026, type is output.
 Q2      = DFFE( D2 $  GND,  LOCK0,  VCC,  VCC,  VCC);

-- Node name is 'Q3' = 'REGL3' 
-- Equation name is 'Q3', location is LC021, type is output.
 Q3      = DFFE( D3 $  GND,  LOCK0,  VCC,  VCC,  VCC);

-- Node name is 'Q4' = 'REGL4' 
-- Equation name is 'Q4', location is LC020, type is output.
 Q4      = DFFE( D4 $  GND,  LOCK0,  VCC,  VCC,  VCC);

-- Node name is 'Q5' = 'REGL5' 
-- Equation name is 'Q5', location is LC019, type is output.
 Q5      = DFFE( D5 $  GND,  LOCK0,  VCC,  VCC,  VCC);

-- Node name is 'Q6' = 'REGL6' 
-- Equation name is 'Q6', location is LC018, type is output.
 Q6      = DFFE( D6 $  GND,  LOCK0,  VCC,  VCC,  VCC);

-- Node name is 'Q7' = 'REGL7' 
-- Equation name is 'Q7', location is LC023, type is output.
 Q7      = DFFE( D7 $  GND,  LOCK0,  VCC,  VCC,  VCC);

-- Node name is 'START' 
-- Equation name is 'START', location is LC024, type is output.
 START   = LCELL( _EQ006 $  GND);
  _EQ006 =  current_state0 & !current_state1 & !LOCK0;



--     Shareable expanders that are duplicated in multiple LABs:
--     (none)




Project Information                            d:\vhdl\work6 adcint\adcint.rpt

** COMPILATION SETTINGS & TIMES **

Processing Menu Commands
------------------------

Design Doctor                             = off

Logic Synthesis:

   Synthesis Type Used                    = Standard

   Default Synthesis Style                = NORMAL

      Logic option settings in 'NORMAL' style for 'MAX7000' family

      DECOMPOSE_GATES                     = on
      DUPLICATE_LOGIC_EXTRACTION          = on
      MINIMIZATION                        = full
      MULTI_LEVEL_FACTORING               = on
      NOT_GATE_PUSH_BACK                  = on
      PARALLEL_EXPANDERS                  = off
      REDUCE_LOGIC                        = on
      REFACTORIZATION                     = on
      REGISTER_OPTIMIZATION               = on
      RESYNTHESIZE_NETWORK                = on
      SLOW_SLEW_RATE                      = off
      SOFT_BUFFER_INSERTION               = on
      SUBFACTOR_EXTRACTION                = on
      TURBO_BIT                           = on
      XOR_SYNTHESIS                       = on
      IGNORE_SOFT_BUFFERS                 = off
      USE_LPM_FOR_AHDL_OPERATORS          = off

   Other logic synthesis settings:

      Automatic Global Clock              = on
      Automatic Global Clear              = on
      Automatic Global Preset             = on
      Automatic Global Output Enable      = on
      Automatic Fast I/O                  = off
      Automatic Register Packing          = off
      Automatic Open-Drain Pins           = on
      Automatic Implement in EAB          = off
      One-Hot State Machine Encoding      = off
      Optimize                            = 5

Default Timing Specifications: None

Cut All Bidir Feedback Timing Paths       = on
Cut All Clear & Preset Timing Paths       = on

Ignore Timing Assignments                 = off

Functional SNF Extractor                  = off

Linked SNF Extractor                      = off
Timing SNF Extractor                      = on
Optimize Timing SNF                       = off
Generate AHDL TDO File                    = off
Fitter Settings                           = NORMAL
Smart Recompile                           = off
Total Recompile                           = off

Interfaces Menu Commands
------------------------

EDIF Netlist Writer                       = off
Verilog Netlist Writer                    = off
VHDL Netlist Writer                       = off

Compilation Times
-----------------

   Compiler Netlist Extractor             00:00:00
   Database Builder                       00:00:00
   Logic Synthesizer                      00:00:00
   Partitioner                            00:00:00
   Fitter                                 00:00:00
   Timing SNF Extractor                   00:00:00
   Assembler                              00:00:00
   --------------------------             --------
   Total Time                             00:00:00


Memory Allocated
-----------------

Peak memory allocated during compilation  = 3,671K