adcint.vhd

ADC0809采样控制电路的实现ADC0809是CMOS的8位A/D转换器

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY ADCINT IS
   PORT (D : IN STD_LOGIC_VECTOR(7 DOWNTO 0); --来自0809转换好的8位数据
       CLK : IN STD_LOGIC;                    --状态机工作时钟
       EOC : IN STD_LOGIC;                    --转换状态指示，低电平表示正在转换
       ALE : OUT STD_LOGIC;                    --8个模拟信号通道地址锁存信号
     START : OUT STD_LOGIC;                   --转换开始信号
        OE : OUT STD_LOGIC;                   --数据输出三态控制信号
      ADDA : OUT STD_LOGIC;                   --信号通道最低位控制信号,ADDA被警告
     LOCK0 : OUT STD_LOGIC;                   --观察数据锁存时钟
         Q : OUT STD_LOGIC_VECTOR(7 DOWNTO 0));      --8位数据输出
END ADCINT;
ARCHITECTURE behav OF ADCINT IS
TYPE states IS (st0,st1,st2,st3,st4);                 --定义各状态子类型
  SIGNAL current_state,next_state : states := st0;
  SIGNAL REGL    :   STD_LOGIC_VECTOR(7 DOWNTO 0);
  SIGNAL LOCK    :   STD_LOGIC;                       --转换后数据输出锁存时钟信号
BEGIN
  ADDA <= '1';        --当ADDA<='0',模拟信号进入通道IN0；当ADDA<='1',则进入通道IN1
  Q <= REGL; LOCK0 <= LOCK;
COM : PROCESS(current_state,EOC) BEGIN                --规定各状态转换方式
 CASE current_state IS 
 WHEN st0 => ALE <='0'; START <= '0'; LOCK <= '0';OE <= '0';
              next_state <= st1;                      --0809初始化
 WHEN st1 => ALE <='1'; START <= '1'; LOCK <= '0';OE <= '0';
              next_state <= st2;                      --启动采样
 WHEN st2 => ALE <='0'; START <= '0'; LOCK <= '0';OE <= '0';
   IF (EOC='1')THEN next_state <= st3;                --EOC=1表明转换结束
   ELSE next_state <=  st2; END IF;                   --转换未结束，继续等待
    WHEN st3 => ALE <='0'; START <= '0'; LOCK <= '0';OE <= '1';
              next_state <= st4;                      --开启OE，输出转换好的数据
    WHEN st4 => ALE <='0'; START <= '0'; LOCK <= '1';OE <= '1';
              next_state <= st0;
    WHEN OTHERS => next_state <= st0;
    END CASE;
END PROCESS COM;
REG: PROCESS (CLK)
BEGIN
  IF(CLK'EVENT AND CLK='1')THEN current_state<=next_state; END IF;
  END PROCESS REG;     --由信号current_state将当前状态值带出此进程：REG
LATCH1: PROCESS (LOCK) --此进程中，在LOCK的上升沿，将转换好的数据锁入
  BEGIN
    IF LOCK='1' AND LOCK'EVENT THEN REGL <= D; END IF;
    END PROCESS LATCH1;
END behav;