freqtest8.rpt

8位十六进制频率计设计 根据频率的定义和频率测量的基本原理

_LC078   = DFFE( _EQ036 $  GND,  _EQ037, !_EQ038,  VCC,  VCC);
  _EQ036 =  _LC034 & !_LC074 &  _LC078 & !_LC079
         #  _LC034 & !_LC074 & !_LC078 &  _LC079
         # !_LC034 &  _LC078;
  _EQ037 =  _LC082 & !_LC085 &  _LC092 & !_LC093;
  _EQ038 = !CLK1HZ & !_LC034;

-- Node name is '|cnt10:L4|:12' = '|cnt10:L4|CQI2' 
-- Equation name is '_LC076', type is buried 
_LC076   = TFFE( _EQ039,  _EQ040, !_EQ041,  VCC,  VCC);
  _EQ039 =  _LC034 & !_LC074 & !_LC076 &  _LC078 &  _LC079
         #  _LC034 &  _LC076 &  _LC078 &  _LC079
         #  _LC034 &  _LC074 &  _LC076;
  _EQ040 =  _LC082 & !_LC085 &  _LC092 & !_LC093;
  _EQ041 = !CLK1HZ & !_LC034;

-- Node name is '|cnt10:L4|:11' = '|cnt10:L4|CQI3' 
-- Equation name is '_LC074', type is buried 
_LC074   = DFFE( _EQ042 $  GND,  _EQ043, !_EQ044,  VCC,  VCC);
  _EQ042 =  _LC034 &  _LC074 & !_LC076 & !_LC078 & !_LC079 &  _X004
         #  _LC034 & !_LC074 &  _LC076 &  _LC078 &  _LC079
         # !_LC034 &  _LC074;
  _X004  = EXP( _LC076 &  _LC078 &  _LC079);
  _EQ043 =  _LC082 & !_LC085 &  _LC092 & !_LC093;
  _EQ044 = !CLK1HZ & !_LC034;

-- Node name is '|cnt10:L5|:14' = '|cnt10:L5|CQI0' 
-- Equation name is '_LC068', type is buried 
_LC068   = DFFE( _EQ045 $  GND,  _EQ046, !_EQ047,  VCC,  VCC);
  _EQ045 =  _LC034 & !_LC066 & !_LC068 &  _LC070 & !_LC071
         #  _LC034 & !_LC068 & !_LC070
         # !_LC034 &  _LC068;
  _EQ046 =  _LC074 & !_LC076 & !_LC078 &  _LC079;
  _EQ047 = !CLK1HZ & !_LC034;

-- Node name is '|cnt10:L5|:13' = '|cnt10:L5|CQI1' 
-- Equation name is '_LC071', type is buried 
_LC071   = DFFE( _EQ048 $  GND,  _EQ049, !_EQ050,  VCC,  VCC);
  _EQ048 =  _LC034 & !_LC068 & !_LC070 &  _LC071
         #  _LC034 &  _LC068 & !_LC070 & !_LC071
         # !_LC034 &  _LC071;
  _EQ049 =  _LC074 & !_LC076 & !_LC078 &  _LC079;
  _EQ050 = !CLK1HZ & !_LC034;

-- Node name is '|cnt10:L5|:12' = '|cnt10:L5|CQI2' 
-- Equation name is '_LC066', type is buried 
_LC066   = TFFE( _EQ051,  _EQ052, !_EQ053,  VCC,  VCC);
  _EQ051 =  _LC034 & !_LC066 &  _LC068 & !_LC070 &  _LC071
         #  _LC034 &  _LC066 &  _LC068 &  _LC071
         #  _LC034 &  _LC066 &  _LC070;
  _EQ052 =  _LC074 & !_LC076 & !_LC078 &  _LC079;
  _EQ053 = !CLK1HZ & !_LC034;

-- Node name is '|cnt10:L5|:11' = '|cnt10:L5|CQI3' 
-- Equation name is '_LC070', type is buried 
_LC070   = DFFE( _EQ054 $  GND,  _EQ055, !_EQ056,  VCC,  VCC);
  _EQ054 =  _LC034 & !_LC066 & !_LC068 &  _LC070 & !_LC071 &  _X005
         #  _LC034 &  _LC066 &  _LC068 & !_LC070 &  _LC071
         # !_LC034 &  _LC070;
  _X005  = EXP( _LC066 &  _LC068 &  _LC071);
  _EQ055 =  _LC074 & !_LC076 & !_LC078 &  _LC079;
  _EQ056 = !CLK1HZ & !_LC034;

-- Node name is '|cnt10:L6|:14' = '|cnt10:L6|CQI0' 
-- Equation name is '_LC058', type is buried 
_LC058   = DFFE( _EQ057 $  GND,  _EQ058, !_EQ059,  VCC,  VCC);
  _EQ057 =  _LC034 & !_LC058 & !_LC060 &  _LC062 & !_LC063
         #  _LC034 & !_LC058 & !_LC062
         # !_LC034 &  _LC058;
  _EQ058 = !_LC066 &  _LC068 &  _LC070 & !_LC071;
  _EQ059 = !CLK1HZ & !_LC034;

-- Node name is '|cnt10:L6|:13' = '|cnt10:L6|CQI1' 
-- Equation name is '_LC063', type is buried 
_LC063   = DFFE( _EQ060 $  GND,  _EQ061, !_EQ062,  VCC,  VCC);
  _EQ060 =  _LC034 & !_LC058 & !_LC062 &  _LC063
         #  _LC034 &  _LC058 & !_LC062 & !_LC063
         # !_LC034 &  _LC063;
  _EQ061 = !_LC066 &  _LC068 &  _LC070 & !_LC071;
  _EQ062 = !CLK1HZ & !_LC034;

-- Node name is '|cnt10:L6|:12' = '|cnt10:L6|CQI2' 
-- Equation name is '_LC060', type is buried 
_LC060   = TFFE( _EQ063,  _EQ064, !_EQ065,  VCC,  VCC);
  _EQ063 =  _LC034 &  _LC058 & !_LC060 & !_LC062 &  _LC063
         #  _LC034 &  _LC058 &  _LC060 &  _LC063
         #  _LC034 &  _LC060 &  _LC062;
  _EQ064 = !_LC066 &  _LC068 &  _LC070 & !_LC071;
  _EQ065 = !CLK1HZ & !_LC034;

-- Node name is '|cnt10:L6|:11' = '|cnt10:L6|CQI3' 
-- Equation name is '_LC062', type is buried 
_LC062   = DFFE( _EQ066 $  GND,  _EQ067, !_EQ068,  VCC,  VCC);
  _EQ066 =  _LC034 & !_LC058 & !_LC060 &  _LC062 & !_LC063 &  _X006
         #  _LC034 &  _LC058 &  _LC060 & !_LC062 &  _LC063
         # !_LC034 &  _LC062;
  _X006  = EXP( _LC058 &  _LC060 &  _LC063);
  _EQ067 = !_LC066 &  _LC068 &  _LC070 & !_LC071;
  _EQ068 = !CLK1HZ & !_LC034;

-- Node name is '|cnt10:L7|:14' = '|cnt10:L7|CQI0' 
-- Equation name is '_LC052', type is buried 
_LC052   = DFFE( _EQ069 $  GND,  _EQ070, !_EQ071,  VCC,  VCC);
  _EQ069 =  _LC034 & !_LC050 & !_LC052 &  _LC054 & !_LC055
         #  _LC034 & !_LC052 & !_LC054
         # !_LC034 &  _LC052;
  _EQ070 =  _LC058 & !_LC060 &  _LC062 & !_LC063;
  _EQ071 = !CLK1HZ & !_LC034;

-- Node name is '|cnt10:L7|:13' = '|cnt10:L7|CQI1' 
-- Equation name is '_LC055', type is buried 
_LC055   = DFFE( _EQ072 $  GND,  _EQ073, !_EQ074,  VCC,  VCC);
  _EQ072 =  _LC034 & !_LC052 & !_LC054 &  _LC055
         #  _LC034 &  _LC052 & !_LC054 & !_LC055
         # !_LC034 &  _LC055;
  _EQ073 =  _LC058 & !_LC060 &  _LC062 & !_LC063;
  _EQ074 = !CLK1HZ & !_LC034;

-- Node name is '|cnt10:L7|:12' = '|cnt10:L7|CQI2' 
-- Equation name is '_LC050', type is buried 
_LC050   = TFFE( _EQ075,  _EQ076, !_EQ077,  VCC,  VCC);
  _EQ075 =  _LC034 & !_LC050 &  _LC052 & !_LC054 &  _LC055
         #  _LC034 &  _LC050 &  _LC052 &  _LC055
         #  _LC034 &  _LC050 &  _LC054;
  _EQ076 =  _LC058 & !_LC060 &  _LC062 & !_LC063;
  _EQ077 = !CLK1HZ & !_LC034;

-- Node name is '|cnt10:L7|:11' = '|cnt10:L7|CQI3' 
-- Equation name is '_LC054', type is buried 
_LC054   = DFFE( _EQ078 $  GND,  _EQ079, !_EQ080,  VCC,  VCC);
  _EQ078 =  _LC034 & !_LC050 & !_LC052 &  _LC054 & !_LC055 &  _X007
         #  _LC034 &  _LC050 &  _LC052 & !_LC054 &  _LC055
         # !_LC034 &  _LC054;
  _X007  = EXP( _LC050 &  _LC052 &  _LC055);
  _EQ079 =  _LC058 & !_LC060 &  _LC062 & !_LC063;
  _EQ080 = !CLK1HZ & !_LC034;

-- Node name is '|cnt10:L8|:14' = '|cnt10:L8|CQI0' 
-- Equation name is '_LC047', type is buried 
_LC047   = DFFE( _EQ081 $  GND,  _EQ082, !_EQ083,  VCC,  VCC);
  _EQ081 =  _LC034 &  _LC036 & !_LC044 & !_LC046 & !_LC047
         #  _LC034 & !_LC036 & !_LC047
         # !_LC034 &  _LC047;
  _EQ082 = !_LC050 &  _LC052 &  _LC054 & !_LC055;
  _EQ083 = !CLK1HZ & !_LC034;

-- Node name is '|cnt10:L8|:13' = '|cnt10:L8|CQI1' 
-- Equation name is '_LC044', type is buried 
_LC044   = DFFE( _EQ084 $  GND,  _EQ085, !_EQ086,  VCC,  VCC);
  _EQ084 =  _LC034 & !_LC036 &  _LC044 & !_LC047
         #  _LC034 & !_LC036 & !_LC044 &  _LC047
         # !_LC034 &  _LC044;
  _EQ085 = !_LC050 &  _LC052 &  _LC054 & !_LC055;
  _EQ086 = !CLK1HZ & !_LC034;

-- Node name is '|cnt10:L8|:12' = '|cnt10:L8|CQI2' 
-- Equation name is '_LC046', type is buried 
_LC046   = TFFE( _EQ087,  _EQ088, !_EQ089,  VCC,  VCC);
  _EQ087 =  _LC034 & !_LC036 &  _LC044 & !_LC046 &  _LC047
         #  _LC034 &  _LC044 &  _LC046 &  _LC047
         #  _LC034 &  _LC036 &  _LC046;
  _EQ088 = !_LC050 &  _LC052 &  _LC054 & !_LC055;
  _EQ089 = !CLK1HZ & !_LC034;

-- Node name is '|cnt10:L8|:11' = '|cnt10:L8|CQI3' 
-- Equation name is '_LC036', type is buried 
_LC036   = DFFE( _EQ090 $  GND,  _EQ091, !_EQ092,  VCC,  VCC);
  _EQ090 =  _LC034 &  _LC036 & !_LC044 & !_LC046 & !_LC047 &  _X008
         #  _LC034 & !_LC036 &  _LC044 &  _LC046 &  _LC047
         # !_LC034 &  _LC036;
  _X008  = EXP( _LC044 &  _LC046 &  _LC047);
  _EQ091 = !_LC050 &  _LC052 &  _LC054 & !_LC055;
  _EQ092 = !CLK1HZ & !_LC034;

-- Node name is '|FTCTRL:L9|:5' = '|FTCTRL:L9|Div2CLK' 
-- Equation name is '_LC034', type is buried 
_LC034   = TFFE( VCC,  CLK1HZ,  VCC,  VCC,  VCC);



--     Shareable expanders that are duplicated in multiple LABs:
--     (none)




Project Information                       d:\vhdl\work5 freqtest\freqtest8.rpt

** COMPILATION SETTINGS & TIMES **

Processing Menu Commands
------------------------

Design Doctor                             = off

Logic Synthesis:

   Synthesis Type Used                    = Standard

   Default Synthesis Style                = NORMAL

      Logic option settings in 'NORMAL' style for 'MAX7000' family

      DECOMPOSE_GATES                     = on
      DUPLICATE_LOGIC_EXTRACTION          = on
      MINIMIZATION                        = full
      MULTI_LEVEL_FACTORING               = on
      NOT_GATE_PUSH_BACK                  = on
      PARALLEL_EXPANDERS                  = off
      REDUCE_LOGIC                        = on
      REFACTORIZATION                     = on
      REGISTER_OPTIMIZATION               = on
      RESYNTHESIZE_NETWORK                = on
      SLOW_SLEW_RATE                      = off
      SOFT_BUFFER_INSERTION               = on
      SUBFACTOR_EXTRACTION                = on
      TURBO_BIT                           = on
      XOR_SYNTHESIS                       = on
      IGNORE_SOFT_BUFFERS                 = off
      USE_LPM_FOR_AHDL_OPERATORS          = off

   Other logic synthesis settings:

      Automatic Global Clock              = on
      Automatic Global Clear              = on
      Automatic Global Preset             = on
      Automatic Global Output Enable      = on
      Automatic Fast I/O                  = off
      Automatic Register Packing          = off
      Automatic Open-Drain Pins           = on
      Automatic Implement in EAB          = off
      One-Hot State Machine Encoding      = off
      Optimize                            = 5

Default Timing Specifications: None

Cut All Bidir Feedback Timing Paths       = on
Cut All Clear & Preset Timing Paths       = on

Ignore Timing Assignments                 = off

Functional SNF Extractor                  = off

Linked SNF Extractor                      = off
Timing SNF Extractor                      = on
Optimize Timing SNF                       = off
Generate AHDL TDO File                    = off
Fitter Settings                           = NORMAL
Smart Recompile                           = off
Total Recompile                           = off

Interfaces Menu Commands
------------------------

EDIF Netlist Writer                       = off
Verilog Netlist Writer                    = off
VHDL Netlist Writer                       = off

Compilation Times
-----------------

   Compiler Netlist Extractor             00:00:01
   Database Builder                       00:00:00
   Logic Synthesizer                      00:00:00
   Partitioner                            00:00:00
   Fitter                                 00:00:00
   Timing SNF Extractor                   00:00:00
   Assembler                              00:00:00
   --------------------------             --------
   Total Time                             00:00:01


Memory Allocated
-----------------

Peak memory allocated during compilation  = 12,057K