📄 freqtest8.rpt
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Project Information d:\vhdl\work5 freqtest\freqtest8.rpt
MAX+plus II Compiler Report File
Version 10.2 07/10/2002
Compiled: 08/30/2008 10:42:19
Copyright (C) 1988-2002 Altera Corporation
Any megafunction design, and related net list (encrypted or decrypted),
support information, device programming or simulation file, and any other
associated documentation or information provided by Altera or a partner
under Altera's Megafunction Partnership Program may be used only to
program PLD devices (but not masked PLD devices) from Altera. Any other
use of such megafunction design, net list, support information, device
programming or simulation file, or any other related documentation or
information is prohibited for any other purpose, including, but not
limited to modification, reverse engineering, de-compiling, or use with
any other silicon devices, unless such use is explicitly licensed under
a separate agreement with Altera or a megafunction partner. Title to
the intellectual property, including patents, copyrights, trademarks,
trade secrets, or maskworks, embodied in any such megafunction design,
net list, support information, device programming or simulation file, or
any other related documentation or information provided by Altera or a
megafunction partner, remains with Altera, the megafunction partner, or
their respective licensors. No other licenses, including any licenses
needed under any third party's intellectual property, are provided herein.
***** Project compilation was successful
FREQTEST8
** DEVICE SUMMARY **
Chip/ Input Output Bidir Shareable
POF Device Pins Pins Pins LCs Expanders % Utilized
freqtest8
EPM7096LC68-7 2 32 0 65 8 67 %
User Pins: 2 32 0
Project Information d:\vhdl\work5 freqtest\freqtest8.rpt
** AUTO GLOBAL SIGNALS **
INFO: Signal 'FSIN' chosen for auto global Clock
Project Information d:\vhdl\work5 freqtest\freqtest8.rpt
** FILE HIERARCHY **
|cnt10:L1|
|cnt10:L1|lpm_add_sub:52|
|cnt10:L1|lpm_add_sub:52|addcore:adder|
|cnt10:L1|lpm_add_sub:52|addcore:adder|addcore:adder0|
|cnt10:L1|lpm_add_sub:52|altshift:result_ext_latency_ffs|
|cnt10:L1|lpm_add_sub:52|altshift:carry_ext_latency_ffs|
|cnt10:L1|lpm_add_sub:52|altshift:oflow_ext_latency_ffs|
|cnt10:L2|
|cnt10:L2|lpm_add_sub:52|
|cnt10:L2|lpm_add_sub:52|addcore:adder|
|cnt10:L2|lpm_add_sub:52|addcore:adder|addcore:adder0|
|cnt10:L2|lpm_add_sub:52|altshift:result_ext_latency_ffs|
|cnt10:L2|lpm_add_sub:52|altshift:carry_ext_latency_ffs|
|cnt10:L2|lpm_add_sub:52|altshift:oflow_ext_latency_ffs|
|cnt10:L3|
|cnt10:L3|lpm_add_sub:52|
|cnt10:L3|lpm_add_sub:52|addcore:adder|
|cnt10:L3|lpm_add_sub:52|addcore:adder|addcore:adder0|
|cnt10:L3|lpm_add_sub:52|altshift:result_ext_latency_ffs|
|cnt10:L3|lpm_add_sub:52|altshift:carry_ext_latency_ffs|
|cnt10:L3|lpm_add_sub:52|altshift:oflow_ext_latency_ffs|
|cnt10:L4|
|cnt10:L4|lpm_add_sub:52|
|cnt10:L4|lpm_add_sub:52|addcore:adder|
|cnt10:L4|lpm_add_sub:52|addcore:adder|addcore:adder0|
|cnt10:L4|lpm_add_sub:52|altshift:result_ext_latency_ffs|
|cnt10:L4|lpm_add_sub:52|altshift:carry_ext_latency_ffs|
|cnt10:L4|lpm_add_sub:52|altshift:oflow_ext_latency_ffs|
|cnt10:L5|
|cnt10:L5|lpm_add_sub:52|
|cnt10:L5|lpm_add_sub:52|addcore:adder|
|cnt10:L5|lpm_add_sub:52|addcore:adder|addcore:adder0|
|cnt10:L5|lpm_add_sub:52|altshift:result_ext_latency_ffs|
|cnt10:L5|lpm_add_sub:52|altshift:carry_ext_latency_ffs|
|cnt10:L5|lpm_add_sub:52|altshift:oflow_ext_latency_ffs|
|cnt10:L6|
|cnt10:L6|lpm_add_sub:52|
|cnt10:L6|lpm_add_sub:52|addcore:adder|
|cnt10:L6|lpm_add_sub:52|addcore:adder|addcore:adder0|
|cnt10:L6|lpm_add_sub:52|altshift:result_ext_latency_ffs|
|cnt10:L6|lpm_add_sub:52|altshift:carry_ext_latency_ffs|
|cnt10:L6|lpm_add_sub:52|altshift:oflow_ext_latency_ffs|
|cnt10:L7|
|cnt10:L7|lpm_add_sub:52|
|cnt10:L7|lpm_add_sub:52|addcore:adder|
|cnt10:L7|lpm_add_sub:52|addcore:adder|addcore:adder0|
|cnt10:L7|lpm_add_sub:52|altshift:result_ext_latency_ffs|
|cnt10:L7|lpm_add_sub:52|altshift:carry_ext_latency_ffs|
|cnt10:L7|lpm_add_sub:52|altshift:oflow_ext_latency_ffs|
|cnt10:L8|
|cnt10:L8|lpm_add_sub:52|
|cnt10:L8|lpm_add_sub:52|addcore:adder|
|cnt10:L8|lpm_add_sub:52|addcore:adder|addcore:adder0|
|cnt10:L8|lpm_add_sub:52|altshift:result_ext_latency_ffs|
|cnt10:L8|lpm_add_sub:52|altshift:carry_ext_latency_ffs|
|cnt10:L8|lpm_add_sub:52|altshift:oflow_ext_latency_ffs|
|ftctrl:L9|
|reg32b:L10|
Device-Specific Information: d:\vhdl\work5 freqtest\freqtest8.rpt
freqtest8
***** Logic for device 'freqtest8' compiled without errors.
Device: EPM7096LC68-7
Device Options:
Turbo Bit = ON
Security Bit = OFF
MultiVolt I/O = OFF
R R R R R R R R R
E E E E E E E E E
S S S S S V S S S S
E E E E E C E E V E E
R R R R R C F R R C R R
V V V G V V I G G G S G V V C V V
E E E N E E N N N N I N E E I E E
D D D D D D T D D D N D D D O D D
-----------------------------------------------------_
/ 9 8 7 6 5 4 3 2 1 68 67 66 65 64 63 62 61 |
RESERVED | 10 60 | DOUT7
VCCIO | 11 59 | DOUT6
RESERVED | 12 58 | GND
CLK1HZ | 13 57 | DOUT5
RESERVED | 14 56 | DOUT4
RESERVED | 15 55 | DOUT10
GND | 16 54 | DOUT11
RESERVED | 17 53 | VCCIO
RESERVED | 18 EPM7096LC68-7 52 | DOUT12
DOUT2 | 19 51 | DOUT13
DOUT1 | 20 50 | DOUT14
VCCIO | 21 49 | DOUT15
DOUT0 | 22 48 | GND
DOUT3 | 23 47 | DOUT8
DOUT30 | 24 46 | DOUT9
DOUT24 | 25 45 | DOUT20
GND | 26 44 | DOUT21
|_ 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 _|
------------------------------------------------------
D D D D V D D G V D D G D D D D V
O O O O C O O N C O O N O O O O C
U U U U C U U D C U U D U U U U C
T T T T I T T I T T T T T T I
2 2 2 2 O 2 3 N 1 1 1 1 2 2 O
5 6 7 8 9 1 T 8 9 6 7 3 2
N.C. = No Connect. This pin has no internal connection to the device.
VCCINT = Dedicated power pin, which MUST be connected to VCC (5.0 volts).
VCCIO = Dedicated power pin, which MUST be connected to VCC (5.0 volts).
GND = Dedicated ground pin or unused dedicated input, which MUST be connected to GND.
RESERVED = Unused I/O pin, which MUST be left unconnected.
Device-Specific Information: d:\vhdl\work5 freqtest\freqtest8.rpt
freqtest8
** RESOURCE USAGE **
Shareable External
Logic Array Block Logic Cells I/O Pins Expanders Interconnect
A: LC1 - LC16 0/16( 0%) 1/ 8( 12%) 0/16( 0%) 0/36( 0%)
B: LC17 - LC32 4/16( 25%) 4/ 8( 50%) 0/16( 0%) 5/36( 13%)
C: LC33 - LC48 13/16( 81%) 8/ 8(100%) 5/16( 31%) 10/36( 27%)
D: LC49 - LC64 16/16(100%) 8/ 8(100%) 10/16( 62%) 14/36( 38%)
E: LC65 - LC80 16/16(100%) 8/ 8(100%) 10/16( 62%) 14/36( 38%)
F: LC81 - LC96 16/16(100%) 4/ 8( 50%) 11/16( 68%) 14/36( 38%)
Total dedicated input pins used: 1/4 ( 25%)
Total I/O pins used: 33/48 ( 68%)
Total logic cells used: 65/96 ( 67%)
Total shareable expanders used: 8/96 ( 8%)
Total Turbo logic cells used: 65/96 ( 67%)
Total shareable expanders not available (n/a): 28/96 ( 29%)
Average fan-in: 5.63
Total fan-in: 366
Total input pins required: 2
Total output pins required: 32
Total bidirectional pins required: 0
Total logic cells required: 65
Total flipflops required: 65
Total product terms required: 230
Total logic cells lending parallel expanders: 0
Total shareable expanders in database: 8
Synthesized logic cells: 0/ 96 ( 0%)
Device-Specific Information: d:\vhdl\work5 freqtest\freqtest8.rpt
freqtest8
** INPUTS **
Shareable
Expanders Fan-In Fan-Out
Pin LC LAB Primitive Code Total Shared n/a INP FBK OUT FBK Name
13 (1) (A) INPUT 0 0 0 0 0 0 33 CLK1HZ
67 - - INPUT G 0 0 0 0 0 0 0 FSIN
Code:
s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
! = NOT gate push-back
r = Fitter-inserted logic cell
G = Global Source. Fan-out destinations counted here do not include destinations
that are driven using global routing resources. Refer to the Auto Global Signals,
Clock Signals, Clear Signals, Synchronous Load Signals, and Synchronous Clear Signals
Sections of this Report File for information on which signals' fan-outs are used as
Clock, Clear, Preset, Output Enable, and synchronous Load signals.
Device-Specific Information: d:\vhdl\work5 freqtest\freqtest8.rpt
freqtest8
** OUTPUTS **
Shareable
Expanders Fan-In Fan-Out
Pin LC LAB Primitive Code Total Shared n/a INP FBK OUT FBK Name
22 19 B FF t 0 0 0 0 2 0 0 DOUT0
20 21 B FF t 0 0 0 0 2 0 0 DOUT1
19 24 B FF t 0 0 0 0 2 0 0 DOUT2
23 17 B FF t 0 0 0 0 2 0 0 DOUT3
56 81 F FF t 0 0 0 0 2 0 0 DOUT4
57 84 F FF t 0 0 0 0 2 0 0 DOUT5
59 86 F FF t 0 0 0 0 2 0 0 DOUT6
60 88 F FF t 0 0 0 0 2 0 0 DOUT7
47 67 E FF t 0 0 0 0 2 0 0 DOUT8
46 65 E FF t 0 0 0 0 2 0 0 DOUT9
55 80 E FF t 0 0 0 0 2 0 0 DOUT10
54 77 E FF t 0 0 0 0 2 0 0 DOUT11
52 75 E FF t 0 0 0 0 2 0 0 DOUT12
51 73 E FF t 0 0 0 0 2 0 0 DOUT13
50 72 E FF t 0 0 0 0 2 0 0 DOUT14
49 69 E FF t 0 0 0 0 2 0 0 DOUT15
39 53 D FF t 0 0 0 0 2 0 0 DOUT16
40 56 D FF t 0 0 0 0 2 0 0 DOUT17
36 49 D FF t 0 0 0 0 2 0 0 DOUT18
37 51 D FF t 0 0 0 0 2 0 0 DOUT19
45 64 D FF t 0 0 0 0 2 0 0 DOUT20
44 61 D FF t 0 0 0 0 2 0 0 DOUT21
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