freqtest.vhd

8位十六进制频率计设计 根据频率的定义和频率测量的基本原理

LIBRARY IEEE;                          -- 频率计顶层设计
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY FREQTEST IS
   PORT ( CLK1Hz : IN STD_LOGIC;
           FSIN  : IN STD_LOGIC;
           DOUT  : OUT STD_LOGIC_VECTOR(31 DOWNTO 0) );
END FREQTEST;
ARCHITECTURE struc OF FREQTEST IS
COMPONENT FTCTRL
   PORT (CLKK : IN STD_LOGIC;           -- 1Hz 
         CNT_EN :  OUT STD_LOGIC;       -- 计算器时钟使能
        RST_CNT :  OUT STD_LOGIC;       -- 计数器清零
          load  :  OUT STD_LOGIC  );    -- 输出锁存信号    
END COMPONENT;
COMPONENT COUNTER32B
   PORT (FIN : IN STD_LOGIC;            -- 时钟信号
         CLR : IN STD_LOGIC;            -- 清零信号
       ENABL : IN STD_LOGIC;            -- 计数器使能信号
        DOUT : OUT STD_LOGIC_VECTOR(31 DOWNTO 0) );   -- 计数结果
END COMPONENT;
COMPONENT REG32B
   PORT (  LK : IN STD_LOGIC;
          DIN : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
         DOUT : OUT STD_LOGIC_VECTOR(31 DOWNTO 0) );
END COMPONENT;
   SIGNAL TSTEN1 : STD_LOGIC;
   SIGNAL CLR_CNT1 : STD_LOGIC;
   SIGNAL Load1  : STD_LOGIC;
   SIGNAL DTO1   : STD_LOGIC_VECTOR(31 DOWNTO 0);
   SIGNAL CARRY_OUT1 : STD_LOGIC_VECTOR(6 DOWNTO 0);
BEGIN
 U1  :    FTCTRL PORT MAP (CLKK => CLK1Hz,CNT_EN => TSTEN1,
                      RST_CNT  => CLR_CNT1,Load => Load1 );
 U2  :    REG32B PORT MAP (  LK => Load1,  DIN => DTO1, DOUT => DOUT);
 U3  :    COUNTER32B PORT MAP (FIN => FSIN , CLR => CLR_CNT1,
                              ENABL => TSTEN1,DOUT => DTO1 );
END struc;