📄 dvf.rpt
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Logic Array Block 'B':
Logic cells placed in LAB 'B'
+----------------------------- LC31 |LPM_ADD_SUB:67|addcore:adder|result_node2
| +--------------------------- LC30 |LPM_ADD_SUB:67|addcore:adder|result_node3
| | +------------------------- LC28 |LPM_ADD_SUB:67|addcore:adder|result_node4
| | | +----------------------- LC27 |LPM_ADD_SUB:67|addcore:adder|result_node5
| | | | +--------------------- LC26 |LPM_ADD_SUB:67|addcore:adder|result_node6
| | | | | +------------------- LC29 |LPM_ADD_SUB:67|addcore:adder|result_node7
| | | | | | +----------------- LC25 FULL
| | | | | | | +--------------- LC24 CNT87
| | | | | | | | +------------- LC17 CNT86
| | | | | | | | | +----------- LC18 CNT85
| | | | | | | | | | +--------- LC19 CNT84
| | | | | | | | | | | +------- LC20 CNT83
| | | | | | | | | | | | +----- LC21 CNT82
| | | | | | | | | | | | | +--- LC22 CNT81
| | | | | | | | | | | | | | +- LC23 CNT80
| | | | | | | | | | | | | | |
| | | | | | | | | | | | | | | Other LABs fed by signals
| | | | | | | | | | | | | | | that feed LAB 'B'
LC | | | | | | | | | | | | | | | | A B | Logic cells that feed LAB 'B':
LC31 -> - - - - - - - - - - - - * - - | - * | <-- |LPM_ADD_SUB:67|addcore:adder|result_node2
LC30 -> - - - - - - - - - - - * - - - | - * | <-- |LPM_ADD_SUB:67|addcore:adder|result_node3
LC28 -> - - - - - - - - - - * - - - - | - * | <-- |LPM_ADD_SUB:67|addcore:adder|result_node4
LC27 -> - - - - - - - - - * - - - - - | - * | <-- |LPM_ADD_SUB:67|addcore:adder|result_node5
LC26 -> - - - - - - - - * - - - - - - | - * | <-- |LPM_ADD_SUB:67|addcore:adder|result_node6
LC29 -> - - - - - - - * - - - - - - - | - * | <-- |LPM_ADD_SUB:67|addcore:adder|result_node7
LC24 -> - - - - - * * * * * * * * * * | - * | <-- CNT87
LC17 -> - - - - * * * * * * * * * * * | - * | <-- CNT86
LC18 -> - - - * * * * * * * * * * * * | - * | <-- CNT85
LC19 -> - - * * * * * * * * * * * * * | - * | <-- CNT84
LC20 -> - * * * * * * * * * * * * * * | - * | <-- CNT83
LC21 -> * * * * * * * * * * * * * * * | - * | <-- CNT82
LC22 -> * * * * * * * * * * * * * * * | - * | <-- CNT81
LC23 -> * * * * * * * * * * * * * * * | - * | <-- CNT80
Pin
43 -> - - - - - - - - - - - - - - - | - - | <-- CLK
12 -> - - - - - - - - - - - - - - * | - * | <-- D0
11 -> - - - - - - - - - - - - - * - | - * | <-- D1
9 -> - - - - - - - - - - - - * - - | - * | <-- D2
8 -> - - - - - - - - - - - * - - - | - * | <-- D3
7 -> - - - - - - - - - - * - - - - | - * | <-- D4
6 -> - - - - - - - - - * - - - - - | - * | <-- D5
5 -> - - - - - - - - * - - - - - - | - * | <-- D6
4 -> - - - - - - - * - - - - - - - | - * | <-- D7
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
Device-Specific Information: d:\vhdl\work4 dvf\dvf.rpt
dvf
** EQUATIONS **
CLK : INPUT;
D0 : INPUT;
D1 : INPUT;
D2 : INPUT;
D3 : INPUT;
D4 : INPUT;
D5 : INPUT;
D6 : INPUT;
D7 : INPUT;
-- Node name is ':153' = 'CNT2'
-- Equation name is 'CNT2', location is LC004, type is buried.
CNT2 = TFFE( VCC, FULL, VCC, VCC, VCC);
-- Node name is ':20' = 'CNT80'
-- Equation name is 'CNT80', location is LC023, type is buried.
CNT80 = TFFE(!_EQ001, GLOBAL( CLK), VCC, VCC, VCC);
_EQ001 = CNT80 & CNT81 & CNT82 & CNT83 & CNT84 & CNT85 & CNT86 &
CNT87 & D0;
-- Node name is ':19' = 'CNT81'
-- Equation name is 'CNT81', location is LC022, type is buried.
CNT81 = TFFE(!_EQ002, GLOBAL( CLK), VCC, VCC, VCC);
_EQ002 = CNT80 & CNT81 & CNT82 & CNT83 & CNT84 & CNT85 & CNT86 &
CNT87 & D1
# !CNT80;
-- Node name is ':18' = 'CNT82'
-- Equation name is 'CNT82', location is LC021, type is buried.
CNT82 = DFFE( _EQ003 $ _LC031, GLOBAL( CLK), VCC, VCC, VCC);
_EQ003 = CNT80 & CNT81 & CNT82 & CNT83 & CNT84 & CNT85 & CNT86 &
CNT87 & D2 & !_LC031
# CNT80 & CNT81 & CNT82 & CNT83 & CNT84 & CNT85 & CNT86 &
CNT87 & !D2 & _LC031;
-- Node name is ':17' = 'CNT83'
-- Equation name is 'CNT83', location is LC020, type is buried.
CNT83 = DFFE( _EQ004 $ _LC030, GLOBAL( CLK), VCC, VCC, VCC);
_EQ004 = CNT80 & CNT81 & CNT82 & CNT83 & CNT84 & CNT85 & CNT86 &
CNT87 & D3 & !_LC030
# CNT80 & CNT81 & CNT82 & CNT83 & CNT84 & CNT85 & CNT86 &
CNT87 & !D3 & _LC030;
-- Node name is ':16' = 'CNT84'
-- Equation name is 'CNT84', location is LC019, type is buried.
CNT84 = DFFE( _EQ005 $ _LC028, GLOBAL( CLK), VCC, VCC, VCC);
_EQ005 = CNT80 & CNT81 & CNT82 & CNT83 & CNT84 & CNT85 & CNT86 &
CNT87 & D4 & !_LC028
# CNT80 & CNT81 & CNT82 & CNT83 & CNT84 & CNT85 & CNT86 &
CNT87 & !D4 & _LC028;
-- Node name is ':15' = 'CNT85'
-- Equation name is 'CNT85', location is LC018, type is buried.
CNT85 = DFFE( _EQ006 $ _LC027, GLOBAL( CLK), VCC, VCC, VCC);
_EQ006 = CNT80 & CNT81 & CNT82 & CNT83 & CNT84 & CNT85 & CNT86 &
CNT87 & D5 & !_LC027
# CNT80 & CNT81 & CNT82 & CNT83 & CNT84 & CNT85 & CNT86 &
CNT87 & !D5 & _LC027;
-- Node name is ':14' = 'CNT86'
-- Equation name is 'CNT86', location is LC017, type is buried.
CNT86 = DFFE( _EQ007 $ _LC026, GLOBAL( CLK), VCC, VCC, VCC);
_EQ007 = CNT80 & CNT81 & CNT82 & CNT83 & CNT84 & CNT85 & CNT86 &
CNT87 & D6 & !_LC026
# CNT80 & CNT81 & CNT82 & CNT83 & CNT84 & CNT85 & CNT86 &
CNT87 & !D6 & _LC026;
-- Node name is ':13' = 'CNT87'
-- Equation name is 'CNT87', location is LC024, type is buried.
CNT87 = DFFE( _EQ008 $ _LC029, GLOBAL( CLK), VCC, VCC, VCC);
_EQ008 = CNT80 & CNT81 & CNT82 & CNT83 & CNT84 & CNT85 & CNT86 &
CNT87 & D7 & !_LC029
# CNT80 & CNT81 & CNT82 & CNT83 & CNT84 & CNT85 & CNT86 &
CNT87 & !D7 & _LC029;
-- Node name is 'FOUT' = ':10'
-- Equation name is 'FOUT', type is output
FOUT = DFFE(!CNT2 $ GND, FULL, VCC, VCC, VCC);
-- Node name is ':12' = 'FULL'
-- Equation name is 'FULL', location is LC025, type is buried.
FULL = DFFE( _EQ009 $ GND, GLOBAL( CLK), VCC, VCC, VCC);
_EQ009 = CNT80 & CNT81 & CNT82 & CNT83 & CNT84 & CNT85 & CNT86 &
CNT87;
-- Node name is '|LPM_ADD_SUB:67|addcore:adder|result_node2' from file "addcore.tdf" line 164, column 16
-- Equation name is '_LC031', type is buried
_LC031 = LCELL( CNT82 $ _EQ010);
_EQ010 = CNT80 & CNT81;
-- Node name is '|LPM_ADD_SUB:67|addcore:adder|result_node3' from file "addcore.tdf" line 164, column 16
-- Equation name is '_LC030', type is buried
_LC030 = LCELL( CNT83 $ _EQ011);
_EQ011 = CNT80 & CNT81 & CNT82;
-- Node name is '|LPM_ADD_SUB:67|addcore:adder|result_node4' from file "addcore.tdf" line 164, column 16
-- Equation name is '_LC028', type is buried
_LC028 = LCELL( CNT84 $ _EQ012);
_EQ012 = CNT80 & CNT81 & CNT82 & CNT83;
-- Node name is '|LPM_ADD_SUB:67|addcore:adder|result_node5' from file "addcore.tdf" line 164, column 16
-- Equation name is '_LC027', type is buried
_LC027 = LCELL( CNT85 $ _EQ013);
_EQ013 = CNT80 & CNT81 & CNT82 & CNT83 & CNT84;
-- Node name is '|LPM_ADD_SUB:67|addcore:adder|result_node6' from file "addcore.tdf" line 164, column 16
-- Equation name is '_LC026', type is buried
_LC026 = LCELL( CNT86 $ _EQ014);
_EQ014 = CNT80 & CNT81 & CNT82 & CNT83 & CNT84 & CNT85;
-- Node name is '|LPM_ADD_SUB:67|addcore:adder|result_node7' from file "addcore.tdf" line 164, column 16
-- Equation name is '_LC029', type is buried
_LC029 = LCELL( CNT87 $ _EQ015);
_EQ015 = CNT80 & CNT81 & CNT82 & CNT83 & CNT84 & CNT85 & CNT86;
-- Shareable expanders that are duplicated in multiple LABs:
-- (none)
Project Information d:\vhdl\work4 dvf\dvf.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Standard
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'MAX7000' family
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
PARALLEL_EXPANDERS = off
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SOFT_BUFFER_INSERTION = on
SUBFACTOR_EXTRACTION = on
TURBO_BIT = on
XOR_SYNTHESIS = on
IGNORE_SOFT_BUFFERS = off
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
One-Hot State Machine Encoding = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:00
Database Builder 00:00:00
Logic Synthesizer 00:00:00
Partitioner 00:00:00
Fitter 00:00:00
Timing SNF Extractor 00:00:00
Assembler 00:00:00
-------------------------- --------
Total Time 00:00:00
Memory Allocated
-----------------
Peak memory allocated during compilation = 3,576K
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