declcnt.rpt

7段数码显示译码器设计7段数码是纯组合电路

t = Turbo logic cell
+ = Synchronous flipflop
! = NOT gate push-back
r = Fitter-inserted logic cell


Device-Specific Information:            c:\vhdl\work3 cnt4b decl7s\declcnt.rpt
declcnt

** LOGIC CELL INTERCONNECTIONS **

Logic Array Block 'B':

                                 Logic cells placed in LAB 'B'
        +----------------------- LC24 |CNT16:L1|CQI3
        | +--------------------- LC25 |CNT16:L1|CQI2
        | | +------------------- LC26 |CNT16:L1|CQI1
        | | | +----------------- LC27 |CNT16:L1|CQI0
        | | | | +--------------- LC19 COUT
        | | | | | +------------- LC18 LED7S0
        | | | | | | +----------- LC17 LED7S1
        | | | | | | | +--------- LC23 LED7S2
        | | | | | | | | +------- LC20 LED7S3
        | | | | | | | | | +----- LC28 LED7S4
        | | | | | | | | | | +--- LC21 LED7S5
        | | | | | | | | | | | +- LC22 LED7S6
        | | | | | | | | | | | | 
        | | | | | | | | | | | |   Other LABs fed by signals
        | | | | | | | | | | | |   that feed LAB 'B'
LC      | | | | | | | | | | | | | A B |     Logic cells that feed LAB 'B':
LC24 -> * - - - * * * * * * * * | - * | <-- |CNT16:L1|CQI3
LC25 -> * * - - * * * * * * * * | - * | <-- |CNT16:L1|CQI2
LC26 -> * * * - * * * * * * * * | - * | <-- |CNT16:L1|CQI1
LC27 -> * * * * * * * * * * * * | - * | <-- |CNT16:L1|CQI0

Pin
43   -> - - - - - - - - - - - - | - - | <-- CLK0
5    -> * * * * - - - - - - - - | - * | <-- EN0
4    -> * * * * - - - - - - - - | - * | <-- RST0


* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).


Device-Specific Information:            c:\vhdl\work3 cnt4b decl7s\declcnt.rpt
declcnt

** EQUATIONS **

CLK0     : INPUT;
EN0      : INPUT;
RST0     : INPUT;

-- Node name is 'COUT' 
-- Equation name is 'COUT', location is LC019, type is output.
 COUT    = LCELL( _EQ001 $  GND);
  _EQ001 =  _LC024 &  _LC025 &  _LC026 &  _LC027;

-- Node name is 'LED7S0' 
-- Equation name is 'LED7S0', location is LC018, type is output.
 LED7S0  = LCELL( _EQ002 $  VCC);
  _EQ002 =  _LC024 &  _LC025 & !_LC026 &  _LC027
         #  _LC024 & !_LC025 &  _LC026 &  _LC027
         # !_LC024 & !_LC025 & !_LC026 &  _LC027
         # !_LC024 &  _LC025 & !_LC026 & !_LC027;

-- Node name is 'LED7S1' 
-- Equation name is 'LED7S1', location is LC017, type is output.
 LED7S1  = LCELL( _EQ003 $  VCC);
  _EQ003 = !_LC024 &  _LC025 & !_LC026 &  _LC027
         #  _LC024 &  _LC026 &  _LC027
         #  _LC025 &  _LC026 & !_LC027;

-- Node name is 'LED7S2' 
-- Equation name is 'LED7S2', location is LC023, type is output.
 LED7S2  = LCELL( _EQ004 $  VCC);
  _EQ004 = !_LC024 & !_LC025 &  _LC026 & !_LC027
         #  _LC024 &  _LC025 &  _LC026
         #  _LC024 &  _LC025 & !_LC027;

-- Node name is 'LED7S3' 
-- Equation name is 'LED7S3', location is LC020, type is output.
 LED7S3  = LCELL( _EQ005 $  VCC);
  _EQ005 =  _LC024 & !_LC025 &  _LC026 & !_LC027
         # !_LC024 & !_LC025 & !_LC026 &  _LC027
         # !_LC024 &  _LC025 & !_LC026 & !_LC027
         #  _LC025 &  _LC026 &  _LC027;

-- Node name is 'LED7S4' 
-- Equation name is 'LED7S4', location is LC028, type is output.
 LED7S4  = LCELL( _EQ006 $  VCC);
  _EQ006 = !_LC024 &  _LC025 & !_LC026
         # !_LC025 & !_LC026 &  _LC027
         # !_LC024 &  _LC027;

-- Node name is 'LED7S5' 
-- Equation name is 'LED7S5', location is LC021, type is output.
 LED7S5  = LCELL( _EQ007 $  VCC);
  _EQ007 =  _LC024 &  _LC025 & !_LC026 &  _LC027
         # !_LC024 & !_LC025 & !_LC026 &  _LC027
         # !_LC024 & !_LC025 &  _LC026 & !_LC027
         # !_LC024 &  _LC026 &  _LC027;

-- Node name is 'LED7S6' 
-- Equation name is 'LED7S6', location is LC022, type is output.
 LED7S6  = LCELL( _EQ008 $  VCC);
  _EQ008 = !_LC024 &  _LC025 &  _LC026 &  _LC027
         #  _LC024 &  _LC025 & !_LC026 & !_LC027
         # !_LC024 & !_LC025 & !_LC026;

-- Node name is '|CNT16:L1|:14' = '|CNT16:L1|CQI0' 
-- Equation name is '_LC027', type is buried 
_LC027   = TFFE( EN0, GLOBAL( CLK0), !RST0,  VCC,  VCC);

-- Node name is '|CNT16:L1|:13' = '|CNT16:L1|CQI1' 
-- Equation name is '_LC026', type is buried 
_LC026   = TFFE( _EQ009, GLOBAL( CLK0), !RST0,  VCC,  VCC);
  _EQ009 =  EN0 &  _LC027;

-- Node name is '|CNT16:L1|:12' = '|CNT16:L1|CQI2' 
-- Equation name is '_LC025', type is buried 
_LC025   = TFFE( _EQ010, GLOBAL( CLK0), !RST0,  VCC,  VCC);
  _EQ010 =  EN0 &  _LC026 &  _LC027;

-- Node name is '|CNT16:L1|:11' = '|CNT16:L1|CQI3' 
-- Equation name is '_LC024', type is buried 
_LC024   = TFFE( _EQ011, GLOBAL( CLK0), !RST0,  VCC,  VCC);
  _EQ011 =  EN0 &  _LC025 &  _LC026 &  _LC027;



--     Shareable expanders that are duplicated in multiple LABs:
--     (none)




Project Information                     c:\vhdl\work3 cnt4b decl7s\declcnt.rpt

** COMPILATION SETTINGS & TIMES **

Processing Menu Commands
------------------------

Design Doctor                             = off

Logic Synthesis:

   Synthesis Type Used                    = Standard

   Default Synthesis Style                = NORMAL

      Logic option settings in 'NORMAL' style for 'MAX7000' family

      DECOMPOSE_GATES                     = on
      DUPLICATE_LOGIC_EXTRACTION          = on
      MINIMIZATION                        = full
      MULTI_LEVEL_FACTORING               = on
      NOT_GATE_PUSH_BACK                  = on
      PARALLEL_EXPANDERS                  = off
      REDUCE_LOGIC                        = on
      REFACTORIZATION                     = on
      REGISTER_OPTIMIZATION               = on
      RESYNTHESIZE_NETWORK                = on
      SLOW_SLEW_RATE                      = off
      SOFT_BUFFER_INSERTION               = on
      SUBFACTOR_EXTRACTION                = on
      TURBO_BIT                           = on
      XOR_SYNTHESIS                       = on
      IGNORE_SOFT_BUFFERS                 = off
      USE_LPM_FOR_AHDL_OPERATORS          = off

   Other logic synthesis settings:

      Automatic Global Clock              = on
      Automatic Global Clear              = on
      Automatic Global Preset             = on
      Automatic Global Output Enable      = on
      Automatic Fast I/O                  = off
      Automatic Register Packing          = off
      Automatic Open-Drain Pins           = on
      Automatic Implement in EAB          = off
      One-Hot State Machine Encoding      = off
      Optimize                            = 5

Default Timing Specifications: None

Cut All Bidir Feedback Timing Paths       = on
Cut All Clear & Preset Timing Paths       = on

Ignore Timing Assignments                 = off

Functional SNF Extractor                  = off

Linked SNF Extractor                      = off
Timing SNF Extractor                      = on
Optimize Timing SNF                       = off
Generate AHDL TDO File                    = off
Fitter Settings                           = NORMAL
Smart Recompile                           = off
Total Recompile                           = off

Interfaces Menu Commands
------------------------

EDIF Netlist Writer                       = off
Verilog Netlist Writer                    = off
VHDL Netlist Writer                       = off

Compilation Times
-----------------

   Compiler Netlist Extractor             00:00:01
   Database Builder                       00:00:00
   Logic Synthesizer                      00:00:00
   Partitioner                            00:00:01
   Fitter                                 00:00:01
   Timing SNF Extractor                   00:00:00
   Assembler                              00:00:00
   --------------------------             --------
   Total Time                             00:00:03


Memory Allocated
-----------------

Peak memory allocated during compilation  = 4,209K