declcnt.rpt

7段数码显示译码器设计7段数码是纯组合电路

Project Information                     c:\vhdl\work3 cnt4b decl7s\declcnt.rpt

MAX+plus II Compiler Report File
Version 10.2 07/10/2002
Compiled: 07/12/2008 21:34:08

Copyright (C) 1988-2002 Altera Corporation
Any megafunction design, and related net list (encrypted or decrypted),
support information, device programming or simulation file, and any other
associated documentation or information provided by Altera or a partner
under Altera's Megafunction Partnership Program may be used only to
program PLD devices (but not masked PLD devices) from Altera.  Any other
use of such megafunction design, net list, support information, device
programming or simulation file, or any other related documentation or
information is prohibited for any other purpose, including, but not
limited to modification, reverse engineering, de-compiling, or use with
any other silicon devices, unless such use is explicitly licensed under
a separate agreement with Altera or a megafunction partner.  Title to
the intellectual property, including patents, copyrights, trademarks,
trade secrets, or maskworks, embodied in any such megafunction design,
net list, support information, device programming or simulation file, or
any other related documentation or information provided by Altera or a
megafunction partner, remains with Altera, the megafunction partner, or
their respective licensors.  No other licenses, including any licenses
needed under any third party's intellectual property, are provided herein.



***** Project compilation was successful


DECLCNT


** DEVICE SUMMARY **

Chip/                     Input   Output   Bidir         Shareable
POF       Device          Pins    Pins     Pins     LCs  Expanders  % Utilized

declcnt   EPM7032LC44-6    3        8        0      12      0           37 %

User Pins:                 3        8        0  



Project Information                     c:\vhdl\work3 cnt4b decl7s\declcnt.rpt

** AUTO GLOBAL SIGNALS **



INFO: Signal 'CLK0' chosen for auto global Clock


Project Information                     c:\vhdl\work3 cnt4b decl7s\declcnt.rpt

** FILE HIERARCHY **



|cnt16:L1|
|cnt16:L1|lpm_add_sub:52|
|cnt16:L1|lpm_add_sub:52|addcore:adder|
|cnt16:L1|lpm_add_sub:52|addcore:adder|addcore:adder0|
|cnt16:L1|lpm_add_sub:52|altshift:result_ext_latency_ffs|
|cnt16:L1|lpm_add_sub:52|altshift:carry_ext_latency_ffs|
|cnt16:L1|lpm_add_sub:52|altshift:oflow_ext_latency_ffs|
|decl7s:L2|


Device-Specific Information:            c:\vhdl\work3 cnt4b decl7s\declcnt.rpt
declcnt

***** Logic for device 'declcnt' compiled without errors.




Device: EPM7032LC44-6

Device Options:
    Turbo Bit                                    = ON
    Security Bit                                 = OFF

              R                                
              E                                
              S                          L  L  
              E                          E  E  
              R     R              C     D  D  
              V  E  S  V  G  G  G  L  G  7  7  
              E  N  T  C  N  N  N  K  N  S  S  
              D  0  0  C  D  D  D  0  D  1  0  
            -----------------------------------_ 
          /   6  5  4  3  2  1 44 43 42 41 40   | 
RESERVED |  7                                39 | COUT 
RESERVED |  8                                38 | LED7S3 
RESERVED |  9                                37 | LED7S5 
     GND | 10                                36 | LED7S6 
RESERVED | 11                                35 | VCC 
RESERVED | 12         EPM7032LC44-6          34 | LED7S2 
RESERVED | 13                                33 | RESERVED 
RESERVED | 14                                32 | RESERVED 
     VCC | 15                                31 | RESERVED 
RESERVED | 16                                30 | GND 
RESERVED | 17                                29 | RESERVED 
         |_  18 19 20 21 22 23 24 25 26 27 28  _| 
           ------------------------------------ 
              R  R  R  R  G  V  R  R  R  R  L  
              E  E  E  E  N  C  E  E  E  E  E  
              S  S  S  S  D  C  S  S  S  S  D  
              E  E  E  E        E  E  E  E  7  
              R  R  R  R        R  R  R  R  S  
              V  V  V  V        V  V  V  V  4  
              E  E  E  E        E  E  E  E     
              D  D  D  D        D  D  D  D     


N.C. = No Connect. This pin has no internal connection to the device.
VCC = Dedicated power pin, which MUST be connected to VCC.
GND = Dedicated ground pin or unused dedicated input, which MUST be connected to GND.
RESERVED = Unused I/O pin, which MUST be left unconnected.



Device-Specific Information:            c:\vhdl\work3 cnt4b decl7s\declcnt.rpt
declcnt

** RESOURCE USAGE **

                                                Shareable     External
Logic Array Block     Logic Cells   I/O Pins    Expanders   Interconnect

A:     LC1 - LC16     0/16(  0%)   2/16( 12%)   0/16(  0%)   0/36(  0%) 
B:    LC17 - LC32    12/16( 75%)   8/16( 50%)   0/16(  0%)   6/36( 16%) 


Total dedicated input pins used:                 1/4      ( 25%)
Total I/O pins used:                            10/32     ( 31%)
Total logic cells used:                         12/32     ( 37%)
Total shareable expanders used:                  0/32     (  0%)
Total Turbo logic cells used:                   12/32     ( 37%)
Total shareable expanders not available (n/a):   0/32     (  0%)
Average fan-in:                                  4.50
Total fan-in:                                    54

Total input pins required:                       3
Total output pins required:                      8
Total bidirectional pins required:               0
Total logic cells required:                     12
Total flipflops required:                        4
Total product terms required:                   33
Total logic cells lending parallel expanders:    0
Total shareable expanders in database:           0

Synthesized logic cells:                         0/  32   (  0%)



Device-Specific Information:            c:\vhdl\work3 cnt4b decl7s\declcnt.rpt
declcnt

** INPUTS **

                                         Shareable
                                         Expanders     Fan-In    Fan-Out
 Pin     LC  LAB  Primitive    Code   Total Shared n/a INP  FBK  OUT  FBK  Name
  43      -   -       INPUT  G            0      0   0    0    0    0    0  CLK0
   5    (2)  (A)      INPUT               0      0   0    0    0    0    4  EN0
   4    (1)  (A)      INPUT               0      0   0    0    0    0    4  RST0


Code:

s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
! = NOT gate push-back
r = Fitter-inserted logic cell
G = Global Source. Fan-out destinations counted here do not include destinations
that are driven using global routing resources. Refer to the Auto Global Signals,
Clock Signals, Clear Signals, Synchronous Load Signals, and Synchronous Clear Signals
Sections of this Report File for information on which signals' fan-outs are used as
Clock, Clear, Preset, Output Enable, and synchronous Load signals.


Device-Specific Information:            c:\vhdl\work3 cnt4b decl7s\declcnt.rpt
declcnt

** OUTPUTS **

                                         Shareable
                                         Expanders     Fan-In    Fan-Out
 Pin     LC  LAB  Primitive    Code   Total Shared n/a INP  FBK  OUT  FBK  Name
  39     19    B     OUTPUT      t        0      0   0    0    4    0    0  COUT
  40     18    B     OUTPUT      t        0      0   0    0    4    0    0  LED7S0
  41     17    B     OUTPUT      t        0      0   0    0    4    0    0  LED7S1
  34     23    B     OUTPUT      t        0      0   0    0    4    0    0  LED7S2
  38     20    B     OUTPUT      t        0      0   0    0    4    0    0  LED7S3
  28     28    B     OUTPUT      t        0      0   0    0    4    0    0  LED7S4
  37     21    B     OUTPUT      t        0      0   0    0    4    0    0  LED7S5
  36     22    B     OUTPUT      t        0      0   0    0    4    0    0  LED7S6


Code:

s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
! = NOT gate push-back
r = Fitter-inserted logic cell


Device-Specific Information:            c:\vhdl\work3 cnt4b decl7s\declcnt.rpt
declcnt

** BURIED LOGIC **

                                         Shareable
                                         Expanders     Fan-In    Fan-Out
 Pin     LC  LAB  Primitive    Code   Total Shared n/a INP  FBK  OUT  FBK  Name
 (33)    24    B       TFFE   +  t        0      0   0    2    3    8    0  |CNT16:L1|CQI3 (|CNT16:L1|:11)
 (32)    25    B       TFFE   +  t        0      0   0    2    2    8    1  |CNT16:L1|CQI2 (|CNT16:L1|:12)
 (31)    26    B       TFFE   +  t        0      0   0    2    1    8    2  |CNT16:L1|CQI1 (|CNT16:L1|:13)
 (29)    27    B       TFFE   +  t        0      0   0    2    0    8    3  |CNT16:L1|CQI0 (|CNT16:L1|:14)


Code:

s = Synthesized pin or logic cell