add8.rpt

组合电路的设计8位加法器设计(ADD8.vhd)

31   -> - - - - - - - - - - * * * - - - | - * | <-- A7
39   -> * * * - * * - - - - - - - * - - | - * | <-- B4
18   -> - - - * * * - - - - - - - - * - | - * | <-- B5
19   -> - - - - - - * * * * - * - - - * | - * | <-- B6
41   -> - - - - - - - - - - * * * - - - | - * | <-- B7
LC8  -> * * * - * * - - - - - - - * - - | - * | <-- |ADD2:L3|~279~1


* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).


Device-Specific Information:                       d:\vhdl\work1 add8\add8.rpt
add8

** EQUATIONS **

A0       : INPUT;
A1       : INPUT;
A2       : INPUT;
A3       : INPUT;
A4       : INPUT;
A5       : INPUT;
A6       : INPUT;
A7       : INPUT;
B0       : INPUT;
B1       : INPUT;
B2       : INPUT;
B3       : INPUT;
B4       : INPUT;
B5       : INPUT;
B6       : INPUT;
B7       : INPUT;
C0       : INPUT;

-- Node name is 'CONT' 
-- Equation name is 'CONT', location is LC001, type is output.
 CONT    = LCELL( _EQ001 $  GND);
  _EQ001 =  _LC027 & !_LC028;

-- Node name is 'S0' 
-- Equation name is 'S0', location is LC006, type is output.
 S0      = LCELL( _EQ002 $  GND);
  _EQ002 =  _LC005 &  _X001;
  _X001  = EXP(!A0 & !B0 & !C0);

-- Node name is 'S1' 
-- Equation name is 'S1', location is LC004, type is output.
 S1      = LCELL( _EQ003 $  GND);
  _EQ003 =  _LC016 &  _X002;
  _X002  = EXP(!A1 & !B1 & !_LC010);

-- Node name is 'S2' 
-- Equation name is 'S2', location is LC007, type is output.
 S2      = LCELL( _EQ004 $  GND);
  _EQ004 =  _LC011 &  _X003;
  _X003  = EXP(!A2 & !B2 & !_LC009);

-- Node name is 'S3' 
-- Equation name is 'S3', location is LC003, type is output.
 S3      = LCELL( _EQ005 $  GND);
  _EQ005 =  _LC014 &  _X004;
  _X004  = EXP(!A3 & !B3 & !_LC013);

-- Node name is 'S4' 
-- Equation name is 'S4', location is LC022, type is output.
 S4      = LCELL( _EQ006 $  GND);
  _EQ006 =  _LC029 &  _X005;
  _X005  = EXP(!A4 & !B4 & !_LC008);

-- Node name is 'S5' 
-- Equation name is 'S5', location is LC021, type is output.
 S5      = LCELL( _EQ007 $  GND);
  _EQ007 =  _LC026 &  _X006;
  _X006  = EXP(!A5 & !B5 & !_LC025);

-- Node name is 'S6' 
-- Equation name is 'S6', location is LC020, type is output.
 S6      = LCELL( _EQ008 $  GND);
  _EQ008 =  _LC019 &  _X007;
  _X007  = EXP(!A6 & !B6 & !_LC023);

-- Node name is 'S7' 
-- Equation name is 'S7', location is LC002, type is output.
 S7      = LCELL( _EQ009 $  GND);
  _EQ009 = !_LC028 &  _LC030;

-- Node name is '|ADD2:L0|~243~1' 
-- Equation name is '_LC005', type is buried 
-- synthesized logic cell 
_LC005   = LCELL( _EQ010 $  A0);
  _EQ010 =  B0 & !C0
         # !B0 &  C0;

-- Node name is '|ADD2:L0|~279~1' 
-- Equation name is '_LC010', type is buried 
-- synthesized logic cell 
_LC010   = LCELL( _EQ011 $  GND);
  _EQ011 = !A0 &  B0 &  C0 &  _X001
         #  A0 &  B0 & !C0 &  _X001
         #  A0 & !B0 &  C0 &  _X001;
  _X001  = EXP(!A0 & !B0 & !C0);

-- Node name is '|ADD2:L1|~243~1' 
-- Equation name is '_LC016', type is buried 
-- synthesized logic cell 
_LC016   = LCELL( _EQ012 $  _LC010);
  _EQ012 = !A1 &  B1
         #  A1 & !B1;

-- Node name is '|ADD2:L1|~279~1' 
-- Equation name is '_LC009', type is buried 
-- synthesized logic cell 
_LC009   = LCELL( _EQ013 $  GND);
  _EQ013 = !A1 &  B1 &  _LC010 &  _X002
         #  A1 &  B1 & !_LC010 &  _X002
         #  A1 & !B1 &  _LC010 &  _X002;
  _X002  = EXP(!A1 & !B1 & !_LC010);

-- Node name is '|ADD2:L2|~243~1' 
-- Equation name is '_LC011', type is buried 
-- synthesized logic cell 
_LC011   = LCELL( _EQ014 $  _LC009);
  _EQ014 = !A2 &  B2
         #  A2 & !B2;

-- Node name is '|ADD2:L2|~279~1' 
-- Equation name is '_LC013', type is buried 
-- synthesized logic cell 
_LC013   = LCELL( _EQ015 $  GND);
  _EQ015 = !A2 &  B2 &  _LC009 &  _X003
         #  A2 &  B2 & !_LC009 &  _X003
         #  A2 & !B2 &  _LC009 &  _X003;
  _X003  = EXP(!A2 & !B2 & !_LC009);

-- Node name is '|ADD2:L3|~243~1' 
-- Equation name is '_LC014', type is buried 
-- synthesized logic cell 
_LC014   = LCELL( _EQ016 $  _LC013);
  _EQ016 = !A3 &  B3
         #  A3 & !B3;

-- Node name is '|ADD2:L3|~279~1' 
-- Equation name is '_LC008', type is buried 
-- synthesized logic cell 
_LC008   = LCELL( _EQ017 $  GND);
  _EQ017 = !A3 &  B3 &  _LC013 &  _X004
         #  A3 &  B3 & !_LC013 &  _X004
         #  A3 & !B3 &  _LC013 &  _X004;
  _X004  = EXP(!A3 & !B3 & !_LC013);

-- Node name is '|ADD2:L4|~243~1' 
-- Equation name is '_LC029', type is buried 
-- synthesized logic cell 
_LC029   = LCELL( _EQ018 $  _LC008);
  _EQ018 = !A4 &  B4
         #  A4 & !B4;

-- Node name is '|ADD2:L4|~275~1' 
-- Equation name is '_LC024', type is buried 
-- synthesized logic cell 
_LC024   = LCELL( _EQ019 $  B4);
  _EQ019 = !A4 & !B4 & !_LC008 &  _LC025
         # !A4 &  B4 & !_LC008
         #  A4 &  _LC008;

-- Node name is '|ADD2:L4|~279~1' 
-- Equation name is '_LC025', type is buried 
-- synthesized logic cell 
_LC025   = LCELL( _EQ020 $  GND);
  _EQ020 = !A4 &  B4 &  _LC008 &  _X005
         #  A4 &  B4 & !_LC008 &  _X005
         #  A4 & !B4 &  _LC008 &  _X005;
  _X005  = EXP(!A4 & !B4 & !_LC008);

-- Node name is '|ADD2:L5|~243~1' 
-- Equation name is '_LC026', type is buried 
-- synthesized logic cell 
_LC026   = LCELL( _EQ021 $  A5);
  _EQ021 =  B5 & !_LC025
         # !B5 &  _LC025;

-- Node name is '|ADD2:L5|~279~1~2' 
-- Equation name is '_LC032', type is buried 
-- synthesized logic cell 
_LC032   = LCELL( _EQ022 $  GND);
  _EQ022 =  A5 &  B5 &  _LC024 &  _X005
         #  A5 &  B5 & !_LC023
         # !A5 & !B5 &  _LC025;
  _X005  = EXP(!A4 & !B4 & !_LC008);

-- Node name is '|ADD2:L5|~279~1' 
-- Equation name is '_LC023', type is buried 
-- synthesized logic cell 
_LC023   = LCELL( _EQ023 $  _LC025);
  _EQ023 =  A5 &  B5 &  _LC024 &  _LC025 &  _X005
         #  A5 &  B5 & !_LC023 &  _LC025
         #  A5 &  B5 & !_LC025
         #  _LC032;
  _X005  = EXP(!A4 & !B4 & !_LC008);

-- Node name is '|ADD2:L6|~237~1' 
-- Equation name is '_LC019', type is buried 
-- synthesized logic cell 
_LC019   = LCELL( _EQ024 $  VCC);
  _EQ024 = !A6 &  B6 &  _LC023 &  _X008
         #  A6 &  B6 & !_LC023 &  _X008
         #  A6 & !B6 &  _LC023 &  _X008
         # !A6 & !B6 & !_LC018 &  _X008;
  _X008  = EXP(!A6 & !B6 &  _LC023);

-- Node name is '|ADD2:L6|~249~1' 
-- Equation name is '_LC018', type is buried 
-- synthesized logic cell 
_LC018   = LCELL( _EQ025 $  GND);
  _EQ025 =  _LC019 &  _X007;
  _X007  = EXP(!A6 & !B6 & !_LC023);

-- Node name is '|ADD2:L6|~272~1' 
-- Equation name is '_LC017', type is buried 
-- synthesized logic cell 
_LC017   = LCELL( _EQ026 $  A6);
  _EQ026 = !A6 & !B6 &  _LC031
         #  A6 & !B6 & !_LC023
         #  B6 &  _LC023;

-- Node name is '|ADD2:L6|~279~1' 
-- Equation name is '_LC031', type is buried 
-- synthesized logic cell 
_LC031   = LCELL( _EQ027 $  GND);
  _EQ027 =  _LC017 &  _X007 &  _X008;
  _X007  = EXP(!A6 & !B6 & !_LC023);
  _X008  = EXP(!A6 & !B6 &  _LC023);

-- Node name is '|ADD2:L7|~243~1' 
-- Equation name is '_LC030', type is buried 
-- synthesized logic cell 
_LC030   = LCELL( _EQ028 $  A7);
  _EQ028 =  B7 & !_LC031
         # !B7 &  _LC031;

-- Node name is '|ADD2:L7|~247~1' 
-- Equation name is '_LC028', type is buried 
-- synthesized logic cell 
_LC028   = LCELL( _EQ029 $ !A7);
  _EQ029 = !A7 &  _LC017 &  _X007 &  _X008
         # !A7 &  B7;
  _X007  = EXP(!A6 & !B6 & !_LC023);
  _X008  = EXP(!A6 & !B6 &  _LC023);

-- Node name is '|ADD2:L7|~276~1' 
-- Equation name is '_LC027', type is buried 
-- synthesized logic cell 
_LC027   = LCELL( _EQ030 $  A7);
  _EQ030 =  A7 & !B7 & !_LC031
         #  B7 &  _LC031;



--     Shareable expanders that are duplicated in multiple LABs:
--     (none)




Project Information                                d:\vhdl\work1 add8\add8.rpt

** COMPILATION SETTINGS & TIMES **

Processing Menu Commands
------------------------

Design Doctor                             = off

Logic Synthesis:

   Synthesis Type Used                    = Standard

   Default Synthesis Style                = NORMAL

      Logic option settings in 'NORMAL' style for 'MAX7000' family

      DECOMPOSE_GATES                     = on
      DUPLICATE_LOGIC_EXTRACTION          = on
      MINIMIZATION                        = full
      MULTI_LEVEL_FACTORING               = on
      NOT_GATE_PUSH_BACK                  = on
      PARALLEL_EXPANDERS                  = off
      REDUCE_LOGIC                        = on
      REFACTORIZATION                     = on
      REGISTER_OPTIMIZATION               = on
      RESYNTHESIZE_NETWORK                = on
      SLOW_SLEW_RATE                      = off
      SOFT_BUFFER_INSERTION               = on
      SUBFACTOR_EXTRACTION                = on
      TURBO_BIT                           = on
      XOR_SYNTHESIS                       = on
      IGNORE_SOFT_BUFFERS                 = off
      USE_LPM_FOR_AHDL_OPERATORS          = off

   Other logic synthesis settings:

      Automatic Global Clock              = on
      Automatic Global Clear              = on
      Automatic Global Preset             = on
      Automatic Global Output Enable      = on
      Automatic Fast I/O                  = off
      Automatic Register Packing          = off
      Automatic Open-Drain Pins           = on
      Automatic Implement in EAB          = off
      One-Hot State Machine Encoding      = off
      Optimize                            = 5

Default Timing Specifications: None

Cut All Bidir Feedback Timing Paths       = on
Cut All Clear & Preset Timing Paths       = on

Ignore Timing Assignments                 = off

Functional SNF Extractor                  = off

Linked SNF Extractor                      = off
Timing SNF Extractor                      = on
Optimize Timing SNF                       = off
Generate AHDL TDO File                    = off
Fitter Settings                           = NORMAL
Smart Recompile                           = off
Total Recompile                           = off

Interfaces Menu Commands
------------------------

EDIF Netlist Writer                       = off
Verilog Netlist Writer                    = off
VHDL Netlist Writer                       = off

Compilation Times
-----------------

   Compiler Netlist Extractor             00:00:00
   Database Builder                       00:00:00
   Logic Synthesizer                      00:00:01
   Partitioner                            00:00:00
   Fitter                                 00:00:00
   Timing SNF Extractor                   00:00:00
   Assembler                              00:00:00
   --------------------------             --------
   Total Time                             00:00:01


Memory Allocated
-----------------

Peak memory allocated during compilation  = 4,430K