d_agc.tan.summary

FPGA数字AGC(帮同学做的毕业设计)

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Timing Analyzer Summary
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Type           : Worst-case tsu
Slack          : N/A
Required Time  : None
Actual Time    : -1.628 ns
From           : reset_IIR
To             : IIR_Filter_2:inst|Samples_out[2][5]
From Clock     : --
To Clock       : sys_clock
Failed Paths   : 0

Type           : Worst-case tco
Slack          : N/A
Required Time  : None
Actual Time    : 33.748 ns
From           : IIR_Filter_2:inst|Samples_out[1][11]
To             : filter_out[19]
From Clock     : sys_clock
To Clock       : --
Failed Paths   : 0

Type           : Worst-case th
Slack          : N/A
Required Time  : None
Actual Time    : 3.226 ns
From           : reset_IIR
To             : IIR_Filter_2:inst|Samples_out[1][9]
From Clock     : --
To Clock       : sys_clock
Failed Paths   : 0

Type           : Clock Setup: 'sys_clock'
Slack          : N/A
Required Time  : None
Actual Time    : 80.43 MHz ( period = 12.433 ns )
From           : IIR_Filter_2:inst|Samples_out[1][3]
To             : IIR_Filter_2:inst|Samples_out[1][15]
From Clock     : sys_clock
To Clock       : sys_clock
Failed Paths   : 0

Type           : Total number of failed paths
Slack          : 
Required Time  : 
Actual Time    : 
From           : 
To             : 
From Clock     : 
To Clock       : 
Failed Paths   : 0

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