judge.v

来自「FPGA数字AGC(帮同学做的毕业设计)」· Verilog 代码 · 共 20 行

module judge(in_data,clock,out_adr);

parameter	judge_min=16'b0100000000000000;
parameter	judge_max=16'b1000000000000000;

input	clock;
input	[15:0]	in_data;

output		out_adr;
reg			out_adr;

always@(posedge clock)
	if(in_data>judge_max)
		out_adr<=1;
	else if(in_data<judge_min)
		out_adr<=0;
	else
		out_adr<=out_adr;
	
endmodule