rom.tan.qmsg

来自「我用VHDL写的正弦」· QMSG 代码 · 共 7 行 · 第 1/5 页

{ "Info" "ITDB_TSU_RESULT" "sld_signaltap:rom1\|trigger_in_reg q1(0) clk 4.758 ns register " "Info: tsu for register \"sld_signaltap:rom1\|trigger_in_reg\" (data pin = \"q1(0)\", clock pin = \"clk\") is 4.758 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "7.647 ns + Longest pin register " "Info: + Longest pin to register delay is 7.647 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.964 ns) 0.964 ns q1(0) 1 PIN PIN_87 1 " "Info: 1: + IC(0.000 ns) + CELL(0.964 ns) = 0.964 ns; Loc. = PIN_87; Fanout = 1; PIN Node = 'q1(0)'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "rom" "UNKNOWN" "V1" "D:/rom/db/rom.quartus_db" { Floorplan "D:/rom/" "" "" { q1(0) } "NODE_NAME" } "" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(6.223 ns) + CELL(0.460 ns) 7.647 ns sld_signaltap:rom1\|trigger_in_reg 2 REG LCFF_X26_Y5_N5 3 " "Info: 2: + IC(6.223 ns) + CELL(0.460 ns) = 7.647 ns; Loc. = LCFF_X26_Y5_N5; Fanout = 3; REG Node = 'sld_signaltap:rom1\|trigger_in_reg'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "rom" "UNKNOWN" "V1" "D:/rom/db/rom.quartus_db" { Floorplan "D:/rom/" "" "6.683 ns" { q1(0) sld_signaltap:rom1|trigger_in_reg } "NODE_NAME" } "" } } { "../altera/quartus51/libraries/megafunctions/sld_signaltap.vhd" "" { Text "D:/altera/quartus51/libraries/megafunctions/sld_signaltap.vhd" 438 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.424 ns ( 18.62 % ) " "Info: Total cell delay = 1.424 ns ( 18.62 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.223 ns ( 81.38 % ) " "Info: Total interconnect delay = 6.223 ns ( 81.38 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "rom" "UNKNOWN" "V1" "D:/rom/db/rom.quartus_db" { Floorplan "D:/rom/" "" "7.647 ns" { q1(0) sld_signaltap:rom1|trigger_in_reg } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "7.647 ns" { q1(0) q1(0)~combout sld_signaltap:rom1|trigger_in_reg } { 0.000ns 0.000ns 6.223ns } { 0.000ns 0.964ns 0.460ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.040 ns + " "Info: + Micro setup delay of destination is -0.040 ns" {  } { { "../altera/quartus51/libraries/megafunctions/sld_signaltap.vhd" "" { Text "D:/altera/quartus51/libraries/megafunctions/sld_signaltap.vhd" 438 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.849 ns - Shortest register " "Info: - Shortest clock path from clock \"clk\" to destination register is 2.849 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.130 ns) 1.130 ns clk 1 CLK PIN_23 1 " "Info: 1: + IC(0.000 ns) + CELL(1.130 ns) = 1.130 ns; Loc. = PIN_23; Fanout = 1; CLK Node = 'clk'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "rom" "UNKNOWN" "V1" "D:/rom/db/rom.quartus_db" { Floorplan "D:/rom/" "" "" { clk } "NODE_NAME" } "" } } { "rom.vhd" "" { Text "D:/rom/rom.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.139 ns) + CELL(0.000 ns) 1.269 ns clk~clkctrl 2 COMB CLKCTRL_G2 171 " "Info: 2: + IC(0.139 ns) + CELL(0.000 ns) = 1.269 ns; Loc. = CLKCTRL_G2; Fanout = 171; COMB Node = 'clk~clkctrl'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "rom" "UNKNOWN" "V1" "D:/rom/db/rom.quartus_db" { Floorplan "D:/rom/" "" "0.139 ns" { clk clk~clkctrl } "NODE_NAME" } "" } } { "rom.vhd" "" { Text "D:/rom/rom.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.914 ns) + CELL(0.666 ns) 2.849 ns sld_signaltap:rom1\|trigger_in_reg 3 REG LCFF_X26_Y5_N5 3 " "Info: 3: + IC(0.914 ns) + CELL(0.666 ns) = 2.849 ns; Loc. = LCFF_X26_Y5_N5; Fanout = 3;