hw3testbench.v

来自「A clock writing by Verilog which can cou」· Verilog 代码 · 共 38 行

`define period 100
`define quarter_period 25 
`timescale 100ms/1ms     //declare the time unit and its precision
`define clk_count 1      //define the clock delay is 1 time unit,i.e. 10ms
module top1();
reg k,clk,reset,Recount_Counter16;
wire [2:0]de;
wire [7:0]seven;
reg [11:0]count;
integer fp1,fp2;     
  clock wwe(k,clk,seven,de,reset);
initial 
  begin
    clk = 0; 
    reset=0;
    k=0;
# (`period+1);reset=1;
# (`period+1);reset=0;
	fp1=$fopen("clock.dat");
	fp2=$fopen("de.dat");
	
	
//# (`period*1440);$stop;	
  end
always begin # (`quarter_period) clk = ~clk;end
always begin # (`period) k = ~k;end
	 always@(posedge clk)
	 begin		 
   	      $fdisplay(fp2,de[2:0]);
	      $fdisplay(fp1,seven[7:0]); 	 
	 end
endmodule