📄 liangzhu.map.rpt
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+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis RAM Summary ;
+---------------------------------------------------------------------+------+------+--------------+--------------+--------------+--------------+------+-------------------+
; Name ; Type ; Mode ; Port A Depth ; Port A Width ; Port B Depth ; Port B Width ; Size ; MIF ;
+---------------------------------------------------------------------+------+------+--------------+--------------+--------------+--------------+------+-------------------+
; altsyncram:reduce_or_rtl_0|altsyncram_kcj:auto_generated|ALTSYNCRAM ; AUTO ; ROM ; 256 ; 6 ; -- ; -- ; 1536 ; liangzhu0.rtl.mif ;
; altsyncram:reduce_or_rtl_1|altsyncram_lcj:auto_generated|ALTSYNCRAM ; AUTO ; ROM ; 128 ; 8 ; -- ; -- ; 1024 ; liangzhu1.rtl.mif ;
+---------------------------------------------------------------------+------+------+--------------+--------------+--------------+--------------+------+-------------------+
+------------------------------------------------------+
; General Register Statistics ;
+----------------------------------------------+-------+
; Statistic ; Value ;
+----------------------------------------------+-------+
; Total registers ; 54 ;
; Number of registers using Synchronous Clear ; 0 ;
; Number of registers using Synchronous Load ; 14 ;
; Number of registers using Asynchronous Clear ; 24 ;
; Number of registers using Asynchronous Load ; 0 ;
; Number of registers using Clock Enable ; 0 ;
; Number of registers using Preset ; 0 ;
+----------------------------------------------+-------+
+-----------------------------------------------------------------------------+
; Parameter Settings for Inferred Entity Instance: altsyncram:reduce_or_rtl_0 ;
+------------------------------------+-------------------+--------------------+
; Parameter Name ; Value ; Type ;
+------------------------------------+-------------------+--------------------+
; BYTE_SIZE_BLOCK ; 8 ; Untyped ;
; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ;
; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ;
; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ;
; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ;
; OPERATION_MODE ; ROM ; Untyped ;
; WIDTH_A ; 6 ; Untyped ;
; WIDTHAD_A ; 8 ; Untyped ;
; NUMWORDS_A ; 256 ; Untyped ;
; OUTDATA_REG_A ; UNREGISTERED ; Untyped ;
; ADDRESS_ACLR_A ; NONE ; Untyped ;
; OUTDATA_ACLR_A ; NONE ; Untyped ;
; WRCONTROL_ACLR_A ; NONE ; Untyped ;
; INDATA_ACLR_A ; NONE ; Untyped ;
; BYTEENA_ACLR_A ; NONE ; Untyped ;
; WIDTH_B ; 1 ; Untyped ;
; WIDTHAD_B ; 1 ; Untyped ;
; NUMWORDS_B ; 1 ; Untyped ;
; INDATA_REG_B ; CLOCK1 ; Untyped ;
; WRCONTROL_WRADDRESS_REG_B ; CLOCK1 ; Untyped ;
; RDCONTROL_REG_B ; CLOCK1 ; Untyped ;
; ADDRESS_REG_B ; CLOCK1 ; Untyped ;
; OUTDATA_REG_B ; UNREGISTERED ; Untyped ;
; BYTEENA_REG_B ; CLOCK1 ; Untyped ;
; INDATA_ACLR_B ; NONE ; Untyped ;
; WRCONTROL_ACLR_B ; NONE ; Untyped ;
; ADDRESS_ACLR_B ; NONE ; Untyped ;
; OUTDATA_ACLR_B ; NONE ; Untyped ;
; RDCONTROL_ACLR_B ; NONE ; Untyped ;
; BYTEENA_ACLR_B ; NONE ; Untyped ;
; WIDTH_BYTEENA_A ; 1 ; Untyped ;
; WIDTH_BYTEENA_B ; 1 ; Untyped ;
; RAM_BLOCK_TYPE ; AUTO ; Untyped ;
; BYTE_SIZE ; 8 ; Untyped ;
; READ_DURING_WRITE_MODE_MIXED_PORTS ; DONT_CARE ; Untyped ;
; INIT_FILE ; liangzhu0.rtl.mif ; Untyped ;
; INIT_FILE_LAYOUT ; PORT_A ; Untyped ;
; MAXIMUM_DEPTH ; 0 ; Untyped ;
; CLOCK_ENABLE_INPUT_A ; NORMAL ; Untyped ;
; CLOCK_ENABLE_INPUT_B ; NORMAL ; Untyped ;
; CLOCK_ENABLE_OUTPUT_A ; NORMAL ; Untyped ;
; CLOCK_ENABLE_OUTPUT_B ; NORMAL ; Untyped ;
; DEVICE_FAMILY ; Cyclone ; Untyped ;
; CBXI_PARAMETER ; altsyncram_kcj ; Untyped ;
+------------------------------------+-------------------+--------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+-----------------------------------------------------------------------------+
; Parameter Settings for Inferred Entity Instance: altsyncram:reduce_or_rtl_1 ;
+------------------------------------+-------------------+--------------------+
; Parameter Name ; Value ; Type ;
+------------------------------------+-------------------+--------------------+
; BYTE_SIZE_BLOCK ; 8 ; Untyped ;
; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ;
; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ;
; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ;
; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ;
; OPERATION_MODE ; ROM ; Untyped ;
; WIDTH_A ; 8 ; Untyped ;
; WIDTHAD_A ; 7 ; Untyped ;
; NUMWORDS_A ; 128 ; Untyped ;
; OUTDATA_REG_A ; UNREGISTERED ; Untyped ;
; ADDRESS_ACLR_A ; NONE ; Untyped ;
; OUTDATA_ACLR_A ; NONE ; Untyped ;
; WRCONTROL_ACLR_A ; NONE ; Untyped ;
; INDATA_ACLR_A ; NONE ; Untyped ;
; BYTEENA_ACLR_A ; NONE ; Untyped ;
; WIDTH_B ; 1 ; Untyped ;
; WIDTHAD_B ; 1 ; Untyped ;
; NUMWORDS_B ; 1 ; Untyped ;
; INDATA_REG_B ; CLOCK1 ; Untyped ;
; WRCONTROL_WRADDRESS_REG_B ; CLOCK1 ; Untyped ;
; RDCONTROL_REG_B ; CLOCK1 ; Untyped ;
; ADDRESS_REG_B ; CLOCK1 ; Untyped ;
; OUTDATA_REG_B ; UNREGISTERED ; Untyped ;
; BYTEENA_REG_B ; CLOCK1 ; Untyped ;
; INDATA_ACLR_B ; NONE ; Untyped ;
; WRCONTROL_ACLR_B ; NONE ; Untyped ;
; ADDRESS_ACLR_B ; NONE ; Untyped ;
; OUTDATA_ACLR_B ; NONE ; Untyped ;
; RDCONTROL_ACLR_B ; NONE ; Untyped ;
; BYTEENA_ACLR_B ; NONE ; Untyped ;
; WIDTH_BYTEENA_A ; 1 ; Untyped ;
; WIDTH_BYTEENA_B ; 1 ; Untyped ;
; RAM_BLOCK_TYPE ; AUTO ; Untyped ;
; BYTE_SIZE ; 8 ; Untyped ;
; READ_DURING_WRITE_MODE_MIXED_PORTS ; DONT_CARE ; Untyped ;
; INIT_FILE ; liangzhu1.rtl.mif ; Untyped ;
; INIT_FILE_LAYOUT ; PORT_A ; Untyped ;
; MAXIMUM_DEPTH ; 0 ; Untyped ;
; CLOCK_ENABLE_INPUT_A ; NORMAL ; Untyped ;
; CLOCK_ENABLE_INPUT_B ; NORMAL ; Untyped ;
; CLOCK_ENABLE_OUTPUT_A ; NORMAL ; Untyped ;
; CLOCK_ENABLE_OUTPUT_B ; NORMAL ; Untyped ;
; DEVICE_FAMILY ; Cyclone ; Untyped ;
; CBXI_PARAMETER ; altsyncram_lcj ; Untyped ;
+------------------------------------+-------------------+--------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+--------------------------------+
; Analysis & Synthesis Equations ;
+--------------------------------+
The equations can be found in F:/例子/实战训练1 2.5 在Altera的FPGA开发板上运行第一个FPGA程序/liangzhu.map.eqn.
+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
Info: Version 5.0 Build 171 11/03/2005 Service Pack 2 SJ Full Version
Info: Processing started: Thu Jun 26 08:18:06 2008
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off liangzhu -c liangzhu
Info: Found 1 design units, including 1 entities, in source file liangzhu.v
Info: Found entity 1: liangzhu
Info: Elaborating entity "liangzhu" for the top level hierarchy
Warning: Reduced register "high[3]" with stuck data_in port to stuck value GND
Warning: Reduced register "high[2]" with stuck data_in port to stuck value GND
Warning: Reduced register "high[1]" with stuck data_in port to stuck value GND
Warning: Reduced register "med[3]" with stuck data_in port to stuck value GND
Warning: Reduced register "low[3]" with stuck data_in port to stuck value GND
Info: Inferred 2 megafunctions from design logic
Info: Inferred altsyncram megafunction (OPERATION_MODE=ROM, NUMWORDS_A=256, WIDTH_A=6) from the following design logic: "reduce_or~33"
Info: Inferred altsyncram megafunction (OPERATION_MODE=ROM, NUMWORDS_A=128, WIDTH_A=8) from the following design logic: "reduce_or~34"
Info: Found 1 design units, including 1 entities, in source file c:/altera/quartus50/libraries/megafunctions/altsyncram.tdf
Info: Found entity 1: altsyncram
Info: Found 1 design units, including 1 entities, in source file db/altsyncram_kcj.tdf
Info: Found entity 1: altsyncram_kcj
Info: Found 1 design units, including 1 entities, in source file db/altsyncram_lcj.tdf
Info: Found entity 1: altsyncram_lcj
Info: Implemented 109 device resources after synthesis - the final resource count might be different
Info: Implemented 2 input pins
Info: Implemented 1 output pins
Info: Implemented 92 logic cells
Info: Implemented 14 RAM segments
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 5 warnings
Info: Processing ended: Thu Jun 26 08:18:08 2008
Info: Elapsed time: 00:00:02
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