📄 clock_1.vht

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	seg_expected(1) <= '0';
	WAIT FOR 16232 ps;
	FOR i IN 1 TO 166
	LOOP
		seg_expected(1) <= '1';
		WAIT FOR 39070 ps;
		seg_expected(1) <= '0';
		WAIT FOR 1829 ps;
		seg_expected(1) <= '1';
		WAIT FOR 845 ps;
		seg_expected(1) <= '0';
		WAIT FOR 18256 ps;
	END LOOP;
	FOR i IN 1 TO 167
	LOOP
		seg_expected(1) <= '1';
		WAIT FOR 39070 ps;
		seg_expected(1) <= '0';
		WAIT FOR 1183 ps;
		seg_expected(1) <= '1';
		WAIT FOR 11292 ps;
		seg_expected(1) <= '0';
		WAIT FOR 8455 ps;
	END LOOP;
	FOR i IN 1 TO 166
	LOOP
		seg_expected(1) <= '1';
		WAIT FOR 39070 ps;
		seg_expected(1) <= '0';
		WAIT FOR 1183 ps;
		seg_expected(1) <= '1';
		WAIT FOR 9731 ps;
		seg_expected(1) <= '0';
		WAIT FOR 10016 ps;
	END LOOP;
	seg_expected(1) <= '1';
	WAIT FOR 39070 ps;
	seg_expected(1) <= '0';
	WAIT FOR 1183 ps;
	seg_expected(1) <= '1';
	WAIT FOR 6990 ps;
	seg_expected(1) <= '0';
	WAIT FOR 462 ps;
	seg_expected(1) <= '1';
	WAIT FOR 4039 ps;
	FOR i IN 1 TO 166
	LOOP
		seg_expected(1) <= '0';
		WAIT FOR 8665 ps;
		seg_expected(1) <= '1';
		WAIT FOR 38485 ps;
		seg_expected(1) <= '0';
		WAIT FOR 2850 ps;
		seg_expected(1) <= '1';
		WAIT FOR 10000 ps;
	END LOOP;
	seg_expected(1) <= '0';
	WAIT FOR 8665 ps;
	FOR i IN 1 TO 500
	LOOP
		seg_expected(1) <= '1';
		WAIT FOR 38485 ps;
		seg_expected(1) <= '0';
		WAIT FOR 21515 ps;
	END LOOP;
	FOR i IN 1 TO 167
	LOOP
		seg_expected(1) <= '1';
		WAIT FOR 38485 ps;
		seg_expected(1) <= '0';
		WAIT FOR 2005 ps;
		seg_expected(1) <= '1';
		WAIT FOR 10845 ps;
		seg_expected(1) <= '0';
		WAIT FOR 8665 ps;
	END LOOP;
	FOR i IN 1 TO 333
	LOOP
		seg_expected(1) <= '1';
		WAIT FOR 38485 ps;
		seg_expected(1) <= '0';
		WAIT FOR 2005 ps;
		seg_expected(1) <= '1';
		WAIT FOR 10000 ps;
		seg_expected(1) <= '0';
		WAIT FOR 9510 ps;
	END LOOP;
	FOR i IN 1 TO 167
	LOOP
		seg_expected(1) <= '1';
		WAIT FOR 38485 ps;
		seg_expected(1) <= '0';
		WAIT FOR 2005 ps;
		seg_expected(1) <= '1';
		WAIT FOR 646 ps;
		seg_expected(1) <= '0';
		WAIT FOR 18864 ps;
	END LOOP;
	FOR i IN 1 TO 166
	LOOP
		seg_expected(1) <= '1';
		WAIT FOR 38485 ps;
		seg_expected(1) <= '0';
		WAIT FOR 1359 ps;
		seg_expected(1) <= '1';
		WAIT FOR 11491 ps;
		seg_expected(1) <= '0';
		WAIT FOR 8665 ps;
	END LOOP;
	FOR i IN 1 TO 167
	LOOP
		seg_expected(1) <= '1';
		WAIT FOR 38485 ps;
		seg_expected(1) <= '0';
		WAIT FOR 1359 ps;
		seg_expected(1) <= '1';
		WAIT FOR 9731 ps;
		seg_expected(1) <= '0';
		WAIT FOR 10425 ps;
	END LOOP;
	FOR i IN 1 TO 83
	LOOP
		seg_expected(1) <= '1';
		WAIT FOR 38485 ps;
		seg_expected(1) <= '0';
		WAIT FOR 2850 ps;
		seg_expected(1) <= '1';
		WAIT FOR 9801 ps;
		seg_expected(1) <= '0';
		WAIT FOR 8864 ps;
	END LOOP;
	seg_expected(1) <= '1';
WAIT;
END PROCESS t_prcs_seg_1;
-- expected seg[0]
t_prcs_seg_0: PROCESS
BEGIN
	seg_expected(0) <= '0';
	WAIT FOR 15013293 ps;
	seg_expected(0) <= '1';
	WAIT FOR 4877 ps;
	FOR i IN 1 TO 333
	LOOP
		seg_expected(0) <= '0';
		WAIT FOR 50000 ps;
		seg_expected(0) <= '1';
		WAIT FOR 10000 ps;
	END LOOP;
	seg_expected(0) <= '0';
	WAIT FOR 49199 ps;
	FOR i IN 1 TO 333
	LOOP
		seg_expected(0) <= '1';
		WAIT FOR 10000 ps;
		seg_expected(0) <= '0';
		WAIT FOR 50000 ps;
	END LOOP;
	FOR i IN 1 TO 167
	LOOP
		seg_expected(0) <= '1';
		WAIT FOR 10801 ps;
		seg_expected(0) <= '0';
		WAIT FOR 49199 ps;
	END LOOP;
	FOR i IN 1 TO 166
	LOOP
		seg_expected(0) <= '1';
		WAIT FOR 801 ps;
		seg_expected(0) <= '0';
		WAIT FOR 9199 ps;
		seg_expected(0) <= '1';
		WAIT FOR 801 ps;
		seg_expected(0) <= '0';
		WAIT FOR 49199 ps;
	END LOOP;
	seg_expected(0) <= '1';
	WAIT FOR 801 ps;
	seg_expected(0) <= '0';
	WAIT FOR 2021 ps;
	seg_expected(0) <= '1';
	WAIT FOR 6308 ps;
	FOR i IN 1 TO 333
	LOOP
		seg_expected(0) <= '0';
		WAIT FOR 50269 ps;
		seg_expected(0) <= '1';
		WAIT FOR 9731 ps;
	END LOOP;
	seg_expected(0) <= '0';
	WAIT FOR 20031671 ps;
	FOR i IN 1 TO 333
	LOOP
		seg_expected(0) <= '1';
		WAIT FOR 10000 ps;
		seg_expected(0) <= '0';
		WAIT FOR 50000 ps;
	END LOOP;
	seg_expected(0) <= '1';
	WAIT FOR 9199 ps;
	FOR i IN 1 TO 333
	LOOP
		seg_expected(0) <= '0';
		WAIT FOR 50000 ps;
		seg_expected(0) <= '1';
		WAIT FOR 10000 ps;
	END LOOP;
	seg_expected(0) <= '0';
	WAIT FOR 50000 ps;
	FOR i IN 1 TO 166
	LOOP
		seg_expected(0) <= '1';
		WAIT FOR 10801 ps;
		seg_expected(0) <= '0';
		WAIT FOR 49199 ps;
	END LOOP;
	seg_expected(0) <= '1';
	WAIT FOR 2822 ps;
	seg_expected(0) <= '0';
	WAIT FOR 7178 ps;
	FOR i IN 1 TO 166
	LOOP
		seg_expected(0) <= '1';
		WAIT FOR 801 ps;
		seg_expected(0) <= '0';
		WAIT FOR 49199 ps;
		seg_expected(0) <= '1';
		WAIT FOR 801 ps;
		seg_expected(0) <= '0';
		WAIT FOR 9199 ps;
	END LOOP;
	seg_expected(0) <= '1';
	WAIT FOR 801 ps;
	seg_expected(0) <= '0';
	WAIT FOR 48598 ps;
	FOR i IN 1 TO 333
	LOOP
		seg_expected(0) <= '1';
		WAIT FOR 9731 ps;
		seg_expected(0) <= '0';
		WAIT FOR 50269 ps;
	END LOOP;
	seg_expected(0) <= '1';
	WAIT FOR 6222 ps;
	seg_expected(0) <= '0';
	WAIT FOR 679 ps;
	seg_expected(0) <= '1';
	WAIT FOR 462 ps;
	seg_expected(0) <= '0';
	WAIT FOR 4039 ps;
	FOR i IN 1 TO 333
	LOOP
		seg_expected(0) <= '1';
		WAIT FOR 8665 ps;
		seg_expected(0) <= '0';
		WAIT FOR 38485 ps;
		seg_expected(0) <= '1';
		WAIT FOR 2850 ps;
		seg_expected(0) <= '0';
		WAIT FOR 10000 ps;
	END LOOP;
	seg_expected(0) <= '1';
	WAIT FOR 8665 ps;
	FOR i IN 1 TO 333
	LOOP
		seg_expected(0) <= '0';
		WAIT FOR 38485 ps;
		seg_expected(0) <= '1';
		WAIT FOR 21515 ps;
	END LOOP;
	FOR i IN 1 TO 333
	LOOP
		seg_expected(0) <= '0';
		WAIT FOR 38485 ps;
		seg_expected(0) <= '1';
		WAIT FOR 12049 ps;
		seg_expected(0) <= '0';
		WAIT FOR 801 ps;
		seg_expected(0) <= '1';
		WAIT FOR 8665 ps;
	END LOOP;
	FOR i IN 1 TO 167
	LOOP
		seg_expected(0) <= '0';
		WAIT FOR 38485 ps;
		seg_expected(0) <= '1';
		WAIT FOR 21515 ps;
	END LOOP;
	FOR i IN 1 TO 167
	LOOP
		seg_expected(0) <= '0';
		WAIT FOR 38485 ps;
		seg_expected(0) <= '1';
		WAIT FOR 2648 ps;
		seg_expected(0) <= '0';
		WAIT FOR 9401 ps;
		seg_expected(0) <= '1';
		WAIT FOR 9466 ps;
	END LOOP;
	FOR i IN 1 TO 333
	LOOP
		seg_expected(0) <= '0';
		WAIT FOR 38485 ps;
		seg_expected(0) <= '1';
		WAIT FOR 11179 ps;
		seg_expected(0) <= '0';
		WAIT FOR 1671 ps;
		seg_expected(0) <= '1';
		WAIT FOR 8665 ps;
	END LOOP;
	FOR i IN 1 TO 83
	LOOP
		seg_expected(0) <= '0';
		WAIT FOR 38485 ps;
		seg_expected(0) <= '1';
		WAIT FOR 2850 ps;
		seg_expected(0) <= '0';
		WAIT FOR 10000 ps;
		seg_expected(0) <= '1';
		WAIT FOR 8665 ps;
	END LOOP;
	seg_expected(0) <= '0';
WAIT;
END PROCESS t_prcs_seg_0;

-- Set trigger on real/expected o/ pattern changes                        

t_prcs_trigger_e : PROCESS(scan_expected,seg_expected)
BEGIN
	trigger_e <= NOT trigger_e;
END PROCESS t_prcs_trigger_e;

t_prcs_trigger_r : PROCESS(scan,seg)
BEGIN
	trigger_r <= NOT trigger_r;
END PROCESS t_prcs_trigger_r;


t_prcs_selfcheck : PROCESS
VARIABLE i : INTEGER := 1;
VARIABLE txt : LINE;

VARIABLE last_scan_exp : STD_LOGIC_VECTOR(5 DOWNTO 0) := "UUUUUU";
VARIABLE last_seg_exp : STD_LOGIC_VECTOR(6 DOWNTO 0) := "UUUUUUU";

VARIABLE on_first_change : trackvec := "11";
BEGIN

WAIT UNTIL (sampler'LAST_VALUE = '1'OR sampler'LAST_VALUE = '0')
	AND sampler'EVENT;
IF (debug_tbench = '1') THEN
	write(txt,string'("Scanning pattern "));
	write(txt,i);
	writeline(output,txt);
	write(txt,string'("| expected "));write(txt,scan_name);write(txt,string'(" = "));write(txt,scan_expected_prev);
	write(txt,string'("| expected "));write(txt,seg_name);write(txt,string'(" = "));write(txt,seg_expected_prev);
	writeline(output,txt);
	write(txt,string'("| real "));write(txt,scan_name);write(txt,string'(" = "));write(txt,scan_prev);
	write(txt,string'("| real "));write(txt,seg_name);write(txt,string'(" = "));write(txt,seg_prev);
	writeline(output,txt);
	i := i + 1;
END IF;
IF ( scan_expected_prev /= "XXXXXX" ) AND (scan_expected_prev /= "UUUUUU" ) AND (scan_prev /= scan_expected_prev) AND (
	(scan_expected_prev /= last_scan_exp) OR
	(on_first_change(1) = '1')
		) THEN
	throw_error("scan",scan_expected_prev,scan_prev);
	num_mismatches(0) <= num_mismatches(0) + 1;
	on_first_change(1) := '0';
	last_scan_exp := scan_expected_prev;
END IF;
IF ( seg_expected_prev /= "XXXXXXX" ) AND (seg_expected_prev /= "UUUUUUU" ) AND (seg_prev /= seg_expected_prev) AND (
	(seg_expected_prev /= last_seg_exp) OR
	(on_first_change(2) = '1')
		) THEN
	throw_error("seg",seg_expected_prev,seg_prev);
	num_mismatches(1) <= num_mismatches(1) + 1;
	on_first_change(2) := '0';
	last_seg_exp := seg_expected_prev;
END IF;
    trigger_i <= NOT trigger_i;
END PROCESS t_prcs_selfcheck;


t_prcs_trigger_res : PROCESS(trigger_e,trigger_i,trigger_r)
BEGIN
	trigger <= trigger_i XOR trigger_e XOR trigger_r;
END PROCESS t_prcs_trigger_res;

t_prcs_endsim : PROCESS
VARIABLE txt : LINE;
VARIABLE total_mismatches : INTEGER := 0;
BEGIN
WAIT FOR 300000000 ps;
total_mismatches := num_mismatches(0) + num_mismatches(1);
IF (total_mismatches = 0) THEN                                              
        write(txt,string'("Simulation passed !"));                        
        writeline(output,txt);                                              
ELSE                                                                        
        write(txt,total_mismatches);                                        
        write(txt,string'(" mismatched vectors : Simulation failed !"));  
        writeline(output,txt);                                              
END IF;                                                                     
WAIT;
END PROCESS t_prcs_endsim;

END ovec_arch;

LIBRARY ieee;                                               
USE ieee.std_logic_1164.all;                                

LIBRARY STD;                                                            
USE STD.textio.ALL;                                                     

USE WORK.clock_1_vhd_tb_types.ALL;                                         

ENTITY clock_1_vhd_vec_tst IS
END clock_1_vhd_vec_tst;
ARCHITECTURE clock_1_arch OF clock_1_vhd_vec_tst IS
-- constants                                                 
-- signals                                                   
SIGNAL clk : STD_LOGIC;
SIGNAL clr : STD_LOGIC;
SIGNAL en : STD_LOGIC;
SIGNAL scan : STD_LOGIC_VECTOR(5 DOWNTO 0);
SIGNAL seg : STD_LOGIC_VECTOR(6 DOWNTO 0);
SIGNAL sampler : sample_type;

COMPONENT clock_1
	PORT (
	clk : IN STD_LOGIC;
	clr : IN STD_LOGIC;
	en : IN STD_LOGIC;
	scan : OUT STD_LOGIC_VECTOR(5 DOWNTO 0);
	seg : OUT STD_LOGIC_VECTOR(6 DOWNTO 0)
	);
END COMPONENT;
COMPONENT clock_1_vhd_check_tst
PORT (
	scan : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
	seg : IN STD_LOGIC_VECTOR(6 DOWNTO 0);
	sampler : IN sample_type
);
END COMPONENT;
COMPONENT clock_1_vhd_sample_tst
PORT (
	clk : IN STD_LOGIC;
	clr : IN STD_LOGIC;
	en : IN STD_LOGIC;
	sampler : OUT sample_type
	);
END COMPONENT;
BEGIN
	i1 : clock_1
	PORT MAP (
-- list connections between master ports and signals
	clk => clk,
	clr => clr,
	en => en,
	scan => scan,
	seg => seg
	);

-- clk
t_prcs_clk: PROCESS
BEGIN
LOOP
	clk <= '0';
	WAIT FOR 5000 ps;
	clk <= '1';
	WAIT FOR 5000 ps;
	FOR i IN 1 TO 29998
	LOOP
		clk <= '0';
		WAIT FOR 5000 ps;
		clk <= '1';
		WAIT FOR 5000 ps;
	END LOOP;
	clk <= '0';
	WAIT FOR 5000 ps;
	clk <= '1';
	WAIT FOR 5000 ps;
	IF (NOW >= 300000000 ps) THEN WAIT; END IF;
END LOOP;
END PROCESS t_prcs_clk;

-- en
t_prcs_en: PROCESS
BEGIN
	en <= '0';
WAIT;
END PROCESS t_prcs_en;

-- clr
t_prcs_clr: PROCESS
BEGIN
	clr <= '0';
WAIT;
END PROCESS t_prcs_clr;
tb_sample : clock_1_vhd_sample_tst
PORT MAP (
	clk => clk,
	clr => clr,
	en => en,
	sampler => sampler
	);

tb_out : clock_1_vhd_check_tst
PORT MAP (
	scan => scan,
	seg => seg,
	sampler => sampler
	);
END clock_1_arch;
上一页 1 2 34
💿 文件大小 462 K
👤 上传用户 ATT320
📂 所属分类 VHDL/FPGA/Verilog
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