📄 clock_1.vht
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-- Copyright (C) 1991-2007 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions
-- and other software and tools, and its AMPP partner logic
-- functions, and any output files from any of the foregoing
-- (including device programming or simulation files), and any
-- associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License
-- Subscription Agreement, Altera MegaCore Function License
-- Agreement, or other applicable license agreement, including,
-- without limitation, that your use is for the sole purpose of
-- programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the
-- applicable agreement for further details.
-- *****************************************************************************
-- This file contains a Vhdl test bench with test vectors .The test vectors
-- are exported from a vector file in the Quartus Waveform Editor and apply to
-- the top level entity of the current Quartus project .The user can use this
-- testbench to simulate his design using a third-party simulation tool .
-- *****************************************************************************
-- Generated on "05/16/2007 15:51:17"
-- Vhdl Self-Checking Test Bench (with test vectors) for design : clock_1
--
-- Simulation tool : 3rd Party
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY STD;
USE STD.textio.ALL;
PACKAGE clock_1_vhd_tb_types IS
-- input port types
-- output port names
CONSTANT scan_name : STRING (1 TO 4) := "scan";
CONSTANT seg_name : STRING (1 TO 3) := "seg";
-- n(outputs)
CONSTANT o_num : INTEGER := 2;
-- mismatches vector type
TYPE mmvec IS ARRAY (0 to (o_num - 1)) OF INTEGER;
-- exp o/ first change track vector type
TYPE trackvec IS ARRAY (1 to o_num) OF BIT;
-- sampler type
SUBTYPE sample_type IS STD_LOGIC;
-- utility functions
FUNCTION std_logic_to_char (a: STD_LOGIC) RETURN CHARACTER;
FUNCTION std_logic_vector_to_string (a: STD_LOGIC_VECTOR) RETURN STRING;
PROCEDURE write (l:INOUT LINE; value:IN STD_LOGIC; justified: IN SIDE:= RIGHT; field:IN WIDTH:=0);
PROCEDURE write (l:INOUT LINE; value:IN STD_LOGIC_VECTOR; justified: IN SIDE:= RIGHT; field:IN WIDTH:=0);
PROCEDURE throw_error(output_port_name: IN STRING; expected_value : IN STD_LOGIC; real_value : IN STD_LOGIC);
PROCEDURE throw_error(output_port_name: IN STRING; expected_value : IN STD_LOGIC_VECTOR; real_value : IN STD_LOGIC_VECTOR);
END clock_1_vhd_tb_types;
PACKAGE BODY clock_1_vhd_tb_types IS
FUNCTION std_logic_to_char (a: STD_LOGIC)
RETURN CHARACTER IS
BEGIN
CASE a IS
WHEN 'U' =>
RETURN 'U';
WHEN 'X' =>
RETURN 'X';
WHEN '0' =>
RETURN '0';
WHEN '1' =>
RETURN '1';
WHEN 'Z' =>
RETURN 'Z';
WHEN 'W' =>
RETURN 'W';
WHEN 'L' =>
RETURN 'L';
WHEN 'H' =>
RETURN 'H';
WHEN '-' =>
RETURN 'D';
END CASE;
END;
FUNCTION std_logic_vector_to_string (a: STD_LOGIC_VECTOR)
RETURN STRING IS
VARIABLE result : STRING(1 TO a'LENGTH);
VARIABLE j : NATURAL := 1;
BEGIN
FOR i IN a'RANGE LOOP
result(j) := std_logic_to_char(a(i));
j := j + 1;
END LOOP;
RETURN result;
END;
PROCEDURE write (l:INOUT LINE; value:IN STD_LOGIC; justified: IN SIDE:=RIGHT; field:IN WIDTH:=0) IS
BEGIN
write(L,std_logic_to_char(VALUE),JUSTIFIED,field);
END;
PROCEDURE write (l:INOUT LINE; value:IN STD_LOGIC_VECTOR; justified: IN SIDE:= RIGHT; field:IN WIDTH:=0) IS
BEGIN
write(L,std_logic_vector_to_string(VALUE),JUSTIFIED,field);
END;
PROCEDURE throw_error(output_port_name: IN STRING; expected_value : IN STD_LOGIC; real_value : IN STD_LOGIC) IS
VARIABLE txt : LINE;
BEGIN
write(txt,string'("ERROR! Vector Mismatch for output port "));
write(txt,output_port_name);
write(txt,string'(" :: @time = "));
write(txt,NOW);
write(txt,string'(", Expected value = "));
write(txt,expected_value);
write(txt,string'(", Real value = "));
write(txt,real_value);
writeline(output,txt);
END;
PROCEDURE throw_error(output_port_name: IN STRING; expected_value : IN STD_LOGIC_VECTOR; real_value : IN STD_LOGIC_VECTOR) IS
VARIABLE txt : LINE;
BEGIN
write(txt,string'("ERROR! Vector Mismatch for output port "));
write(txt,output_port_name);
write(txt,string'(" :: @time = "));
write(txt,NOW);
write(txt,string'(", Expected value = "));
write(txt,expected_value);
write(txt,string'(", Real value = "));
write(txt,real_value);
writeline(output,txt);
END;
END clock_1_vhd_tb_types;
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE WORK.clock_1_vhd_tb_types.ALL;
ENTITY clock_1_vhd_sample_tst IS
PORT (
clk : IN STD_LOGIC;
clr : IN STD_LOGIC;
en : IN STD_LOGIC;
sampler : OUT sample_type
);
END clock_1_vhd_sample_tst;
ARCHITECTURE sample_arch OF clock_1_vhd_sample_tst IS
SIGNAL tbo_int_sample_clk : sample_type := '1';
BEGIN
t_prcs_sample : PROCESS ( clk , clr , en )
BEGIN
IF (NOW > 0 ps) AND (NOW < 300000000 ps) THEN
tbo_int_sample_clk <= NOT tbo_int_sample_clk ;
END IF;
END PROCESS t_prcs_sample;
sampler <= tbo_int_sample_clk;
END sample_arch;
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY STD;
USE STD.textio.ALL;
USE WORK.clock_1_vhd_tb_types.ALL;
ENTITY clock_1_vhd_check_tst IS
GENERIC (
debug_tbench : BIT := '0'
);
PORT (
scan : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
seg : IN STD_LOGIC_VECTOR(6 DOWNTO 0);
sampler : IN sample_type
);
END clock_1_vhd_check_tst;
ARCHITECTURE ovec_arch OF clock_1_vhd_check_tst IS
SIGNAL scan_expected,scan_expected_prev,scan_prev : STD_LOGIC_VECTOR(5 DOWNTO 0);
SIGNAL seg_expected,seg_expected_prev,seg_prev : STD_LOGIC_VECTOR(6 DOWNTO 0);
SIGNAL trigger : BIT := '0';
SIGNAL trigger_e : BIT := '0';
SIGNAL trigger_r : BIT := '0';
SIGNAL trigger_i : BIT := '0';
SIGNAL num_mismatches : mmvec := (OTHERS => 0);
BEGIN
-- Update history buffers expected /o
t_prcs_update_o_expected_hist : PROCESS (trigger)
BEGIN
scan_expected_prev <= scan_expected;
seg_expected_prev <= seg_expected;
END PROCESS t_prcs_update_o_expected_hist;
-- Update history buffers real /o
t_prcs_update_o_real_hist : PROCESS (trigger)
BEGIN
scan_prev <= scan;
seg_prev <= seg;
END PROCESS t_prcs_update_o_real_hist;
-- expected scan[5]
t_prcs_scan_5: PROCESS
BEGIN
LOOP
scan_expected(5) <= '0';
WAIT FOR 44309 ps;
FOR i IN 1 TO 4999
LOOP
scan_expected(5) <= '1';
WAIT FOR 170 ps;
scan_expected(5) <= '0';
WAIT FOR 10000 ps;
scan_expected(5) <= '1';
WAIT FOR 9830 ps;
scan_expected(5) <= '0';
WAIT FOR 40000 ps;
END LOOP;
scan_expected(5) <= '1';
WAIT FOR 170 ps;
scan_expected(5) <= '0';
WAIT FOR 10000 ps;
scan_expected(5) <= '1';
WAIT FOR 5521 ps;
IF (NOW >= 300000000 ps) THEN WAIT; END IF;
END LOOP;
END PROCESS t_prcs_scan_5;
-- expected scan[4]
t_prcs_scan_4: PROCESS
BEGIN
LOOP
scan_expected(4) <= '0';
WAIT FOR 43909 ps;
FOR i IN 1 TO 4999
LOOP
scan_expected(4) <= '1';
WAIT FOR 10000 ps;
scan_expected(4) <= '0';
WAIT FOR 50000 ps;
END LOOP;
scan_expected(4) <= '1';
WAIT FOR 10000 ps;
scan_expected(4) <= '0';
WAIT FOR 6091 ps;
IF (NOW >= 300000000 ps) THEN WAIT; END IF;
END LOOP;
END PROCESS t_prcs_scan_4;
-- expected scan[3]
t_prcs_scan_3: PROCESS
BEGIN
LOOP
scan_expected(3) <= '0';
WAIT FOR 33689 ps;
FOR i IN 1 TO 4999
LOOP
scan_expected(3) <= '1';
WAIT FOR 10000 ps;
scan_expected(3) <= '0';
WAIT FOR 50000 ps;
END LOOP;
scan_expected(3) <= '1';
WAIT FOR 10000 ps;
scan_expected(3) <= '0';
WAIT FOR 16311 ps;
IF (NOW >= 300000000 ps) THEN WAIT; END IF;
END LOOP;
END PROCESS t_prcs_scan_3;
-- expected scan[2]
t_prcs_scan_2: PROCESS
BEGIN
LOOP
scan_expected(2) <= '0';
WAIT FOR 24629 ps;
FOR i IN 1 TO 4999
LOOP
scan_expected(2) <= '1';
WAIT FOR 10000 ps;
scan_expected(2) <= '0';
WAIT FOR 50000 ps;
END LOOP;
scan_expected(2) <= '1';
WAIT FOR 10000 ps;
scan_expected(2) <= '0';
WAIT FOR 25371 ps;
IF (NOW >= 300000000 ps) THEN WAIT; END IF;
END LOOP;
END PROCESS t_prcs_scan_2;
-- expected scan[1]
t_prcs_scan_1: PROCESS
BEGIN
LOOP
scan_expected(1) <= '0';
WAIT FOR 14179 ps;
FOR i IN 1 TO 4999
LOOP
scan_expected(1) <= '1';
WAIT FOR 9816 ps;
scan_expected(1) <= '0';
WAIT FOR 20000 ps;
scan_expected(1) <= '1';
WAIT FOR 352 ps;
scan_expected(1) <= '0';
WAIT FOR 29832 ps;
END LOOP;
scan_expected(1) <= '1';
WAIT FOR 9816 ps;
scan_expected(1) <= '0';
WAIT FOR 20000 ps;
scan_expected(1) <= '1';
WAIT FOR 352 ps;
scan_expected(1) <= '0';
WAIT FOR 15653 ps;
IF (NOW >= 300000000 ps) THEN WAIT; END IF;
END LOOP;
END PROCESS t_prcs_scan_1;
-- expected scan[0]
t_prcs_scan_0: PROCESS
BEGIN
LOOP
scan_expected(0) <= '1';
WAIT FOR 14490 ps;
FOR i IN 1 TO 4999
LOOP
scan_expected(0) <= '0';
WAIT FOR 50000 ps;
scan_expected(0) <= '1';
WAIT FOR 10000 ps;
END LOOP;
scan_expected(0) <= '0';
WAIT FOR 45510 ps;
IF (NOW >= 300000000 ps) THEN WAIT; END IF;
END LOOP;
END PROCESS t_prcs_scan_0;
-- expected seg[6]
t_prcs_seg_6: PROCESS
BEGIN
seg_expected(6) <= '1';
WAIT FOR 5048033 ps;
FOR i IN 1 TO 166
LOOP
seg_expected(6) <= '0';
WAIT FOR 10000 ps;
seg_expected(6) <= '1';
WAIT FOR 50000 ps;
END LOOP;
seg_expected(6) <= '0';
WAIT FOR 2223 ps;
seg_expected(6) <= '1';
WAIT FOR 20037175 ps;
FOR i IN 1 TO 166
LOOP
seg_expected(6) <= '0';
WAIT FOR 10000 ps;
seg_expected(6) <= '1';
WAIT FOR 50000 ps;
END LOOP;
seg_expected(6) <= '0';
WAIT FOR 2825 ps;
seg_expected(6) <= '1';
WAIT FOR 7175 ps;
FOR i IN 1 TO 166
LOOP
seg_expected(6) <= '0';
WAIT FOR 602 ps;
seg_expected(6) <= '1';
WAIT FOR 49398 ps;
seg_expected(6) <= '0';
WAIT FOR 602 ps;
seg_expected(6) <= '1';
WAIT FOR 9398 ps;
END LOOP;
seg_expected(6) <= '0';
WAIT FOR 602 ps;
seg_expected(6) <= '1';
WAIT FOR 49398 ps;
FOR i IN 1 TO 167
LOOP
seg_expected(6) <= '0';
WAIT FOR 801 ps;
seg_expected(6) <= '1';
WAIT FOR 59199 ps;
END LOOP;
FOR i IN 1 TO 166
LOOP
seg_expected(6) <= '0';
WAIT FOR 602 ps;
seg_expected(6) <= '1';
WAIT FOR 59398 ps;
END LOOP;
seg_expected(6) <= '0';
WAIT FOR 602 ps;
seg_expected(6) <= '1';
WAIT FOR 10028446 ps;
FOR i IN 1 TO 166
LOOP
seg_expected(6) <= '0';
WAIT FOR 1554 ps;
seg_expected(6) <= '1';
WAIT FOR 58446 ps;
END LOOP;
seg_expected(6) <= '0';
WAIT FOR 1554 ps;
seg_expected(6) <= '1';
WAIT FOR 47525 ps;
FOR i IN 1 TO 166
LOOP
seg_expected(6) <= '0';
WAIT FOR 2475 ps;
seg_expected(6) <= '1';
WAIT FOR 10000 ps;
seg_expected(6) <= '0';
WAIT FOR 8455 ps;
seg_expected(6) <= '1';
WAIT FOR 39070 ps;
END LOOP;
seg_expected(6) <= '0';
WAIT FOR 2475 ps;
seg_expected(6) <= '1';
WAIT FOR 2223 ps;
seg_expected(6) <= '0';
WAIT FOR 16232 ps;
FOR i IN 1 TO 166
LOOP
seg_expected(6) <= '1';
WAIT FOR 39070 ps;
seg_expected(6) <= '0';
WAIT FOR 20930 ps;
END LOOP;
FOR i IN 1 TO 167
LOOP
seg_expected(6) <= '1';
WAIT FOR 39070 ps;
seg_expected(6) <= '0';
WAIT FOR 2475 ps;
seg_expected(6) <= '1';
WAIT FOR 10199 ps;
seg_expected(6) <= '0';
WAIT FOR 8256 ps;
END LOOP;
FOR i IN 1 TO 166
LOOP
seg_expected(6) <= '1';
WAIT FOR 39070 ps;
seg_expected(6) <= '0';
WAIT FOR 2674 ps;
seg_expected(6) <= '1';
WAIT FOR 10000 ps;
seg_expected(6) <= '0';
WAIT FOR 8256 ps;
END LOOP;
seg_expected(6) <= '1';
WAIT FOR 39070 ps;
seg_expected(6) <= '0';
WAIT FOR 2674 ps;
seg_expected(6) <= '1';
WAIT FOR 5123 ps;
seg_expected(6) <= '0';
WAIT FOR 4076 ps;
FOR i IN 1 TO 166
LOOP
seg_expected(6) <= '1';
WAIT FOR 602 ps;
seg_expected(6) <= '0';
WAIT FOR 8455 ps;
seg_expected(6) <= '1';
WAIT FOR 39070 ps;
seg_expected(6) <= '0';
WAIT FOR 1873 ps;
seg_expected(6) <= '1';
WAIT FOR 602 ps;
seg_expected(6) <= '0';
WAIT FOR 9398 ps;
END LOOP;
seg_expected(6) <= '1';
WAIT FOR 602 ps;
seg_expected(6) <= '0';
WAIT FOR 8455 ps;
FOR i IN 1 TO 167
LOOP
seg_expected(6) <= '1';
WAIT FOR 39070 ps;
seg_expected(6) <= '0';
WAIT FOR 1873 ps;
seg_expected(6) <= '1';
WAIT FOR 10000 ps;
seg_expected(6) <= '0';
WAIT FOR 9057 ps;
END LOOP;
FOR i IN 1 TO 333
LOOP
seg_expected(6) <= '1';
WAIT FOR 39070 ps;
seg_expected(6) <= '0';
WAIT FOR 1873 ps;
seg_expected(6) <= '1';
WAIT FOR 10801 ps;
seg_expected(6) <= '0';
WAIT FOR 8256 ps;
END LOOP;
FOR i IN 1 TO 167
LOOP
seg_expected(6) <= '1';
WAIT FOR 39070 ps;
seg_expected(6) <= '0';
WAIT FOR 1190 ps;
seg_expected(6) <= '1';
WAIT FOR 11285 ps;
seg_expected(6) <= '0';
WAIT FOR 8455 ps;
END LOOP;
FOR i IN 1 TO 166
LOOP
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