clock_1.sdc

简易数字钟

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#
# Generated by : Version 7.0 Build 33 02/05/2007 SJ Full Version
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# Project      : clock_1
# Revision     : clock_1
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# Date         : Sun May 13 15:34:04 中国标准时间 2007
#
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# WARNING: Expected CUT_OFF_PATHS_BETWEEN_CLOCK_DOMAINS to be set to 'OFF', but it is set to 'ON'
#          In SDC, all clocks are related by default
# WARNING: Expected ENABLE_CLOCK_LATENCY to be set to 'ON', but it is set to 'OFF'
#          In SDC, create_generated_clock auto-generates clock latency
# WARNING: Expected DEFAULT_HOLD_MULTICYCLE to be set to 'ONE', but it is set to 'SAME AS MULTICYCLE'
#          In SDC, the Default Hold Multicycle is zero - equivalent to one in the Classic Timing Analyzer
#
# ------------------------------------------
#
# Create generated clocks based on PLLs
derive_pll_clocks -use_tan_name
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# ------------------------------------------
# --------------
# Represent unkown external clock as N/C (Not a Clock)
create_clock -name "N/C" -period 10.0
# --------------
# QSF: -name TCO_REQUIREMENT 10 ns -from clk -to scan[0]
set_output_delay 0.0 -clock "N/C" [get_ports {scan[0]}]
set_max_delay 10 -from {clk} -to [get_ports {scan[0]}]
# QSF: -name TCO_REQUIREMENT 10 ns -from clk -to scan[1]
set_output_delay 0.0 -clock "N/C" [get_ports {scan[1]}]
set_max_delay 10 -from {clk} -to [get_ports {scan[1]}]
# QSF: -name TCO_REQUIREMENT 10 ns -from clk -to scan[2]
set_output_delay 0.0 -clock "N/C" [get_ports {scan[2]}]
set_max_delay 10 -from {clk} -to [get_ports {scan[2]}]
# QSF: -name TCO_REQUIREMENT 10 ns -from clk -to scan[3]
set_output_delay 0.0 -clock "N/C" [get_ports {scan[3]}]
set_max_delay 10 -from {clk} -to [get_ports {scan[3]}]
# QSF: -name TCO_REQUIREMENT 10 ns -from clk -to scan[4]
set_output_delay 0.0 -clock "N/C" [get_ports {scan[4]}]
set_max_delay 10 -from {clk} -to [get_ports {scan[4]}]
# QSF: -name TCO_REQUIREMENT 10 ns -from clk -to scan[5]
set_output_delay 0.0 -clock "N/C" [get_ports {scan[5]}]
set_max_delay 10 -from {clk} -to [get_ports {scan[5]}]