rx_cnt_fifo.vhd

在通讯领域中使用相当广泛的HDLC

    regInst9: FD1S3DX
        PORT MAP (
        Q                    =>  eEqReg14,
        CD                   =>  Reset,
        CK                   =>  RdClock,
        D                    =>  eEqReg04);

    WrAddrGen_ffInst7: FD1S3DX
        PORT MAP (
        Q                    =>  wCntQ7,
        CD                   =>  Reset,
        CK                   =>  WrClock,
        D                    =>  wad7);

    RdAddrGen_xorGB7_I000000: VHI
        PORT MAP (
        Z                    =>  RdAddrGen_xorGB7_VCC);

    RdAddrGen_ffInst2: FD1S3DX
        PORT MAP (
        Q                    =>  RdAddress2,
        CD                   =>  Reset,
        CK                   =>  RdClock,
        D                    =>  rCntGBQ2);

    aeSub_vgbAdderInst1_Sub1: FSUB2
        PORT MAP (
        S1                   =>  aeSubOut7,
        S0                   =>  aeSubOut6,
        BOUT1                =>  aeSub_Cout8,
        BOUT0                =>  aeSub_vgbAdderInst1_tmp1,
        BI                   =>  aeSub_vgbAdderInst1_Cout0,
        B1                   =>  rCntNBQ7,
        B0                   =>  rCntNBQ6,
        A1                   =>  eEqmsb,
        A0                   =>  aeSub6);

    afLEInst_I000000: VLO
        PORT MAP (
        Z                    =>  afLEInst_GND);

    aeSubXor4_inst1: ORCALUT4
        GENERIC MAP (
        INIT => X"6000")
        PORT MAP (
        Z                    =>  aeSub4,
        D                    =>  aeSubXor4_VCC,
        C                    =>  aeSubXor4_VCC,
        B                    =>  aeSub5,
        A                    =>  eEqReg14);

    WrAddrGen_ffInst8: FD1S3DX
        PORT MAP (
        Q                    =>  wCntQ8,
        CD                   =>  Reset,
        CK                   =>  WrClock,
        D                    =>  wad8);

    WrAddrGen_xorGB3_inst1: ORCALUT4
        GENERIC MAP (
        INIT => X"6000")
        PORT MAP (
        Z                    =>  WrAddrGen_BINQ3,
        D                    =>  WrAddrGen_xorGB3_VCC,
        C                    =>  WrAddrGen_xorGB3_VCC,
        B                    =>  WrAddrGen_BINQ4,
        A                    =>  WrAddress3);

    WrAddrGen_xorBG7_inst1: ORCALUT4
        GENERIC MAP (
        INIT => X"6000")
        PORT MAP (
        Z                    =>  wad7,
        D                    =>  WrAddrGen_xorBG7_VCC,
        C                    =>  WrAddrGen_xorBG7_VCC,
        B                    =>  wad8,
        A                    =>  wCntNBQ7);

    I000001: VLO
        PORT MAP (
        Z                    =>  GND);

    fullEQ_xnor4BitEQ0_inst_0: FADD2
        PORT MAP (
        S1                   =>  fullEQ_xnor4BitEQ0_temp1,
        S0                   =>  fullEQ_xnor4BitEQ0_temp0,
        COUT1                =>  fullEQ_Cout0,
        COUT0                =>  fullEQ_xnor4BitEQ0_temp2,
        CI                   =>  fullEQ_VCC,
        B1                   =>  fullEQ_xnor4BitEQ0_GND,
        B0                   =>  fullEQ_xnor4BitEQ0_GND,
        A1                   =>  fullEQ_xnor4BitEQ0_Int1,
        A0                   =>  fullEQ_xnor4BitEQ0_Int0);

    RdAddrGen_ffInst3: FD1S3DX
        PORT MAP (
        Q                    =>  RdAddress3,
        CD                   =>  Reset,
        CK                   =>  RdClock,
        D                    =>  rCntGBQ3);

    RdAddrGen_xorGB2_inst1: ORCALUT4
        GENERIC MAP (
        INIT => X"6000")
        PORT MAP (
        Z                    =>  RdAddrGen_BINQ2,
        D                    =>  RdAddrGen_xorGB2_VCC,
        C                    =>  RdAddrGen_xorGB2_VCC,
        B                    =>  RdAddrGen_BINQ3,
        A                    =>  RdAddress2);

    RdAddrGen_xorBG6_inst1: ORCALUT4
        GENERIC MAP (
        INIT => X"6000")
        PORT MAP (
        Z                    =>  rCntGBQ6,
        D                    =>  RdAddrGen_xorBG6_VCC,
        C                    =>  RdAddrGen_xorBG6_VCC,
        B                    =>  rCntNBQ7,
        A                    =>  rCntNBQ6);

    afLEInst_I000001: VHI
        PORT MAP (
        Z                    =>  afLEInst_VCC);

    RdAddrGen_ffInst4: FD1S3DX
        PORT MAP (
        Q                    =>  RdAddress4,
        CD                   =>  Reset,
        CK                   =>  RdClock,
        D                    =>  rCntGBQ4);

    WrAddrGen_xorBG0_inst1: ORCALUT4
        GENERIC MAP (
        INIT => X"6000")
        PORT MAP (
        Z                    =>  wCntGBQ0,
        D                    =>  WrAddrGen_xorBG0_VCC,
        C                    =>  WrAddrGen_xorBG0_VCC,
        B                    =>  wCntNBQ1,
        A                    =>  wCntNBQ0);

    emptySEQ_xnorremEQ0_inst0: ORCALUT4
        GENERIC MAP (
        INIT => X"9000")
        PORT MAP (
        Z                    =>  emptySEQ_xnorremEQ0_Int0,
        D                    =>  emptySEQ_xnorremEQ0_VCC,
        C                    =>  emptySEQ_xnorremEQ0_VCC,
        B                    =>  eEqReg18,
        A                    =>  rad8);

    fullEQ_xnor4BitEQ1_inst0: ORCALUT4
        GENERIC MAP (
        INIT => X"9009")
        PORT MAP (
        Z                    =>  fullEQ_xnor4BitEQ1_Int0,
        D                    =>  fEqReg15,
        C                    =>  wCntGBQ5,
        B                    =>  fEqReg14,
        A                    =>  wCntGBQ4);

    RdAddrGen_ffInst5: FD1S3DX
        PORT MAP (
        Q                    =>  RdAddress5,
        CD                   =>  Reset,
        CK                   =>  RdClock,
        D                    =>  rCntGBQ5);

    afLEInst_agbInst0: ALEB2
        PORT MAP (
        LE                   =>  afLEInst_agbOut0,
        CI                   =>  afLEInst_VCC,
        B1                   =>  VCC,
        B0                   =>  GND,
        A1                   =>  afSubOut1,
        A0                   =>  afSubOut0);

    emptyEQ_I000000: VHI
        PORT MAP (
        Z                    =>  emptyEQ_VCC);

    afLEInst_agbInst1: ALEB2
        PORT MAP (
        LE                   =>  afLEInst_agbOut1,
        CI                   =>  afLEInst_agbOut0,
        B1                   =>  VCC,
        B0                   =>  GND,
        A1                   =>  afSubOut3,
        A0                   =>  afSubOut2);

    fullEQ_xnor4BitEQ0_I000000: VLO
        PORT MAP (
        Z                    =>  fullEQ_xnor4BitEQ0_GND);

    RdAddrGen_xorGB6_inst1: ORCALUT4
        GENERIC MAP (
        INIT => X"6000")
        PORT MAP (
        Z                    =>  RdAddrGen_BINQ6,
        D                    =>  RdAddrGen_xorGB6_VCC,
        C                    =>  RdAddrGen_xorGB6_VCC,
        B                    =>  RdAddrGen_BINQ7,
        A                    =>  RdAddress6);

    afLEInst_agbInst2: ALEB2
        PORT MAP (
        LE                   =>  afLEInst_agbOut2,
        CI                   =>  afLEInst_agbOut1,
        B1                   =>  VCC,
        B0                   =>  VCC,
        A1                   =>  afSubOut5,
        A0                   =>  afSubOut4);

    afSubXor1_I000000: VHI
        PORT MAP (
        Z                    =>  afSubXor1_VCC);

    RdAddrGen_xorBG3_inst1: ORCALUT4
        GENERIC MAP (
        INIT => X"6000")
        PORT MAP (
        Z                    =>  rCntGBQ3,
        D                    =>  RdAddrGen_xorBG3_VCC,
        C                    =>  RdAddrGen_xorBG3_VCC,
        B                    =>  rCntNBQ4,
        A                    =>  rCntNBQ3);

    afSubXnor_inst_0: FADD2
        PORT MAP (
        S1                   =>  afSubXnor_temp1,
        S0                   =>  afSubXnor_temp0,
        COUT1                =>  afSubXnor_temp2,
        COUT0                =>  afSub8,
        CI                   =>  VCC,
        B1                   =>  afSubXnor_GND,
        B0                   =>  afSubXnor_GND,
        A1                   =>  afSubXnor_GND,
        A0                   =>  afSubXnor_Int0);

    afLEInst_agbInst3: ALEB2
        PORT MAP (
        LE                   =>  afLEInst_agbOut3,
        CI                   =>  afLEInst_agbOut2,
        B1                   =>  VCC,
        B0                   =>  VCC,
        A1                   =>  afSubOut7,
        A0                   =>  afSubOut6);

    afSubXor3_I000000: VHI
        PORT MAP (
        Z                    =>  afSubXor3_VCC);

    WrAddrGen_cAdder_vgbAdderInst0_Adder0: FADD2
        PORT MAP (
        S1                   =>  wCntNBQ1,
        S0                   =>  wCntNBQ0,
        COUT1                =>  WrAddrGen_cAdder_vgbAdderInst0_Cout0,
        COUT0                =>  WrAddrGen_cAdder_vgbAdderInst0_tmp0,
        CI                   =>  WrAddrGen_GND,
        B1                   =>  WrAddrGen_GND,
        B0                   =>  WrEnOut,
        A1                   =>  WrAddrGen_BINQ1,
        A0                   =>  WrAddrGen_BINQ0);

    afLEInst_agbInst4: ALEB2
        PORT MAP (
        LE                   =>  afLEOut,
        CI                   =>  afLEInst_agbOut3,
        B1                   =>  afLEInst_GND,
        B0                   =>  GND,
        A1                   =>  afLEInst_GND,
        A0                   =>  afSubOut8);

    afSub_vgbAdderInst1_Sub0: FSUB2
        PORT MAP (
        S1                   =>  afSubOut5,
        S0                   =>  afSubOut4,
        BOUT1                =>  afSub_vgbAdderInst1_Cout0,
        BOUT0                =>  afSub_vgbAdderInst1_tmp0,
        BI                   =>  afSub_Cout4,
        B1                   =>  wCntNBQ5,
        B0                   =>  wCntNBQ4,
        A1                   =>  afSub5,
        A0                   =>  afSub4);

    WrAddrGen_cAdder_vgbAdderInst0_Adder1: FADD2
        PORT MAP (
        S1                   =>  wCntNBQ3,
        S0                   =>  wCntNBQ2,
        COUT1                =>  WrAddrGen_cAdder_Cout4,
        COUT0                =>  WrAddrGen_cAdder_vgbAdderInst0_tmp1,
        CI                   =>  WrAddrGen_cAdder_vgbAdderInst0_Cout0,
        B1                   =>  WrAddrGen_GND,
        B0                   =>  WrAddrGen_GND,
        A1                   =>  WrAddrGen_BINQ3,
        A0                   =>  WrAddrGen_BINQ2);

    afSubXor4_I000000: VHI
        PORT MAP (
        Z                    =>  afSubXor4_VCC);

    afSubXor6_inst1: ORCALUT4
        GENERIC MAP (
        INIT => X"6000")
        PORT MAP (
        Z                    =>  afSub6,
        D                    =>  afSubXor6_VCC,
        C                    =>  afSubXor6_VCC,
        B                    =>  fEqmsb,
        A                    =>  fEqReg16);

    afSub_vgbAdderInst1_Sub1: FSUB2
        PORT MAP (
        S1                   =>  afSubOut7,
        S0                   =>  afSubOut6,
        BOUT1                =>  afSub_Cout8,
        BOUT0                =>  afSub_vgbAdderInst1_tmp1,
        BI                   =>  afSub_vgbAdderInst1_Cout0,
        B1                   =>  wCntNBQ7,
        B0                   =>  wCntNBQ6,
        A1                   =>  fEqmsb,
        A0                   =>  afSub6);

    WrAddrGen_cAdder_vgbAdderInst2_Adder: FADD2
        PORT MAP (
        S1                   =>  WrAddrGen_cAdder_vgbAdderInst2_tmp0,
        S0                   =>  WrAddrGen_NBQ8,
        COUT1                =>  WrAddrGen_cAdder_vgbAdderInst2_tmp1,
        CI                   =>